An embedded ultra low power nonvolatile memory in a standard CMOS logic process

2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC

Volumn , Issue , 2008, Pages

  Li, Y L ^a   Feng, P ^a   Wu, N J ^a  

^a INSTITUTE OF SEMICONDUCTORS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BIT CELLS; BODY EFFECTS; CHARGE PUMPS; CLOCK FREQUENCIES; CORE AREAS; FLOATING GATES; MEASURED RESULTS; NEW HIGHS; NON-VOLATILE MEMORIES; OPERATING SCHEMES; OUTPUT VOLTAGES; POWER CONSUMPTION; POWER EFFICIENCIES; POWER SUPPLIES; PROTOTYPE CHIPS; RETENTION CHARACTERISTICS; STAGE NUMBERS; STANDARD CMOS; ULTRA-LOW-POWER;

ELECTRIC POWER UTILIZATION; LOGIC CIRCUITS; STANDARDS;

SOLID STATE DEVICES;

EID: 63249111828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2008.4760657     Document Type: Conference Paper

References (7)

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