Design of a real-time face detection parallel architecture using high-level synthesis

Eurasip Journal on Embedded Systems

Volumn 2008, Issue 1, 2008, Pages

  Mamalet, Franck ^a   Farrugia, Nicolas ^a   Roux, Sébastien ^a   Yang, Fan ^b   Paindavoine, Michel ^b  

^a ORANGE LABS   (France)

^b UNIVERSITÉ DE BOURGOGNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 62749204416     PISSN: 16873955     EISSN: 16873963     Source Type: Journal    
DOI: 10.1155/2008/938256     Document Type: Article

References (17)

1. Yang M.-H., Kriegman D. J., Ahuja N., Detecting faces in images: a survey IEEE Transactions on Pattern Analysis and Machine Intelligence 2002 24 1 34 58
2. Garcia C., Delakis M., Convolutional Face Finder: a neural architecture for fast and robust face detection IEEE Transactions on Pattern Analysis and Machine Intelligence 2004 26 11 1408 1423
3. Roux S., Mamalet F., Garcia C., Embedded Convolutional Face Finder Proceedings of IEEE International Conference on Multimedia and Expo (ICME 06) July 2006 Toronto, Canada 285 288
4. Theocharides T., Link G., Vijaykrishnan N., Irwin M. J., Wolf W., Embedded hardware face detection Proceedings of the 17th IEEE International Conference on VLSI Design (VLSID 04) January 2004 Mumbai, India 133 138
5. Nguyen D., Halupka D., Aarabi P., Sheikholeslami A., Real-time face detection and lip feature extraction using field-programmable gate arrays IEEE Transactions on Systems, Man, and Cybernetics 2006 36 4 902 912
6. Farrugia N., Mamalet F., Roux S., Yang F., Paindavoine M., A parallel face detection system implemented on FPGA Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 07) May 2007 New Orleans, La, USA 3704 3707
7. Kathail V., Aditya S., Schreiber R., Ramakrishna Rau B., Cronquist D. C., Sivaraman M., PICO: automatically designing custom computers Computer 2002 35 9 39 47
8. McCloud S., Using a catapult c-based flow to speed implementation and increase flexibility 2003 Wilsonville, Ore, USA Mentor Graphics
9. Dk design suite datasheet. Agility Design System Inc., http://agilityds.com/literature/dkdatasheet01000hqscreen.pdf
10. Coussy P., Corre G., Bomel P., Senn E., Martin E., High-level synthesis under I/O timing and memory constraints 1 Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 05) May 2005 Kobe, Japan 680 683
11. Aug I., Ptrot F., Donnet F., Gomez P., Platform-based design from parallel C specifications IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2005 24 12 1811 1826
12. LeCun Y., Bengio Y., Convolutional networks for images, speech, and time-series The Handbook of Brain Theory and Neural Networks 1998 Cambridge, Mass, USA MIT Press 255 258
13. Girbal S., Vasilache N., Bastoul C., Semi-automatic composition of loop transformations for deep parallelism and memory hierarchies International Journal of Parallel Programming 2006 34 3 261 317
14. Virtex-4 user guide, chap. 5: Configurable logic blocks (clbs). June 2008, http://www.xilinx.com/
15. Kianzad V., Saha S., Schlessman J., An architectural level design methodology for embedded face detection Proceedings of the 3rd International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 05) September 2005 Jersey City, NJ, USA 136 141
16. McCready R., Real-time face detection on a configurable hardware system Proceedings of the 10th International Conference on Field-Programmable Logic and Applications (FPL 00) August 2000 Villach, Austria 157 162
17. Hori Y., Shimizu K., Nakamura Y., Kuroda T., A real-time multi face detection technique using positive-negative lines-of-face template 1 Proceedings of the 17th International Conference on Pattern Recognition (ICPR 04) August 2004 Cambridge, UK 765 768