A parallel face detection system implemented on FPGA

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3704-3707

  Farrugia, Nicolas ^a   Mamalet, Franck ^a   Roux, Sébastien ^a   Yang, Fan ^b   Paindavoine, Michel ^b  

^a ORANGE LABS   (France)

^b UNIVERSITÉ DE BOURGOGNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARALLEL PROCESSING SYSTEMS;

ALGORITHM PARALLELIZATION; ARCHITECTURE ALGORITHM ADEQUATION (AAA); CONVOLUTIONAL FACE FINDER (CFF) ALGORITHMS;

FACE RECOGNITION;

EID: 34548845584     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378647     Document Type: Conference Paper

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