High-level synthesis under I/O timing and memory constraints

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 680-683

  Coussy, Philippe ^a   Corre, Gwenole ^a   Bomel, Pierre ^a   Senn, Eric ^a   Martin, Eric ^a  

^a CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX SYSTEMS; DEDICATED HARDWARE; DSP ALGORITHM; FFT ALGORITHM; FORMAL MODEL; GENERIC ARCHITECTURE; HIGH LEVEL SYNTHESIS; INTERNAL MEMORY; MEMORY ACCESS; MEMORY CONSTRAINTS;

TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 66349118857     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464679     Document Type: Conference Paper

References (10)

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3. Codesimulink, http://polimage.polito.it/groups/codesimulink.html
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9. G. Corre, E. Senn, and al., "Memory accesses Management During High Level Synthesis", In Proc. of CODES-ISSS, 2004.
10. GAUT - HLS Tool for DSP, http://lester.univ-ubs.fr:8080/