Mask defect printability in the spacer patterning process

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7122, Issue , 2008, Pages

  Miyoshi, Seiro ^a   Yamaguchi, Shinji ^a   Hirano, Takashi ^a   Mashita, Hiromitsu ^a   Mukai, Hidefumi ^a   Kobiki, Ayumi ^a   Kobayashi, Yuuji ^a   Hashimoto, Kohji ^a   Inoue, Soichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Acceptable mask defect size; LWR; Mask defect printability; MEF; Spacer patterning process

Indexed keywords

ACCEPTABLE MASK DEFECT SIZE; LWR; MASK DEFECT PRINTABILITY; MEF; SPACER PATTERNING PROCESS;

ETCHING; PHOTORESISTORS; PHOTORESISTS; ROUGHNESS MEASUREMENT;

DEFECTS;

EID: 62649096172     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.801410     Document Type: Conference Paper

References (5)

1. W.-Y. Jung, C.-D. Kim, J.-D. Eom, S.-Y. Cho, S.-M. Jeon, J.-H. Kim, J.-I. Moon, B.-S. Lee, and S.-K. Park, "Patterning with spacer for expanding the resolution limit of current lithography tool." Proc. SPIE Vol. 6156, pp. 61561J-1-9(2006).
2. H. Mukai, E. Shiobara, S. Takahashi, and K. Hashimoto, "A study of CD budget in spacer patterning technology." Proc. SPIE Vol. 6924, pp. 692406-1-8 (2008).
3. H. Mukai, Y. Kobayashi, S. Yamaguchi, K. Kawano, and K. Hashimoto, "A study of mask specification in spacer patterning technology." Proc. SPIE Vol. 7028, pp. 702812-1-8 (2008).
4. S. Yamaguchi, E. Yamanaka, H. Morinaga, K. Hashimoto, T. Sakamoto, A. Hamaguchi, S. Matsumoto, O. Ikenaga, and S. Inoue, "Mask defect specifications with fail-bit-map analysis." Proc. SPIE Vol. 4889, pp. 826-835 (2002).
5. International Technology Roadmap for Semiconductors (ITRS) 2007 Edition, Lithography, Table LITH5a (http://www.itrs.net/Links/2007ITRS/2007-Chapters/ 2007-Lithography.pdf).