Fully integrated SONOS flash memory cell array with BT (body tied)-finFET structure

IEEE Transactions on Nanotechnology

Volumn 5, Issue 3, 2006, Pages 174-178

  Sung, Suk Kang ^b   Kim, Tae Yong ^b   Cho, Eun Suk ^b   Cho, Hye Jin ^b,c   Choi, Byung Yong ^b   Oh, Chang Woo ^b   Cho, Byung Kyu ^b,c   Lee, Choong Ho ^b   Park, Donggun ^a,b,d  

^a IEEE

^b SAMSUNG Electronics   (South Korea)

^c Device Research Team   (South Korea)

^d Research and Development Center   (Japan)

Author keywords

Erase; FinFET; NOR flash; Program; Retention; SONOS; Threshold voltage

Indexed keywords

CHANNEL IMPLANTATION PROCESS; ERASE; FINFET; NOR FLASH; PROGRAM; SONOS;

CELLS; CHANNEL CAPACITY; DIFFUSION; DOPING (ADDITIVES); ELECTRON TUNNELING; MODULATION; RADIO INTERFERENCE; SILICON; THRESHOLD VOLTAGE;

FLASH MEMORY;

EID: 33646754062     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2006.869954     Document Type: Conference Paper

References (9)

1. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
2. T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFET's using bulk Si wafers," in VLSI Symp. Tech. Dig., 2003, pp. 135-136.
3. E. S. Cho, T. Y. Kim, and C. H. Lee, "Optimized cell structure for FinFET array flash memory," in Proc. ESSDERC, 2004, pp. 289-292.
4. F. R. Libsch and M. H. White, "Nonvolatile semiconductor memory technology," in SONOS Nonvolatile Semiconductor Memories, W. D. Brown and J. E. Brewer, Eds. New York: IEEE Press, 1998, pp. 309-357.
5. P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, "FinFET SONOS flash memory for embedded applications," in IEDM. Tech. Dig., 2003, pp. 609-612.
6. M. Specht, R. Kömmling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rösner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Städele, V. Klandievski, E. Hartmann, and L. Risch, "Sub-40 nm tri-gate charge trapping nonvolatile memory cells for high-density applications," in VLSI Symp. Tech. Dig., 2004, pp. 244-245.
7. C. W. Oh, S. D. Suk, Y. K. Lee, S. K. Sung, J.-D. Choe, S.-Y. Lee, D. U. Choi, K. H. Yeo, M. S. Kim, S.-M. Kim, M. Li, S. H. Kim, E.-J. Yoon, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, "Damascene gaet FinFET SONOS memory implemented on bulk silicon wafer," in IEDM. Tech. Dig., 2004, pp. 893-896.
8. I. H. Cho, T. Park, S. Y. Choi, J. D. Lee, and J.-H. Lee, "Body-Tied double-gate SONOS flash memory device built on bulk Si wafer," in DRC Tech. Dig., 2003, pp. 133-134.
9. C. H. Lee, J. M. Yoon, C. Lee, H. M. Yang, K. N. Kim, T. Y. Kim, H. S. Kang, Y. J. Ahn, D. Park, and K. Kim, "Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60 nm technology and beyond," in VLSI Symp. Tech. Dig., 2004, pp. 130-131.