A comparison between 63nm 8Gb and 90nm 4Gb multi-level cell NAND flash memory for mass storage application

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 13-16

  Byeon, Dae Seok ^a   Lee, Sung Soo ^a   Lim, Young Ho ^a   Kang, Dongku ^a   Han, Wook Kee ^a   Kim, Dong Hwan ^a   Suh, Kang Deog ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; NAND CIRCUITS; OPTIMIZATION; SPURIOUS SIGNAL NOISE; TRANSISTORS;

MASS STORAGE APPLICATION; MULTI-LEVEL CELL (MLC); SIGNAL SPEED; TWO-MAT-CELL-ARRAY ARCHITECTURE;

SEMICONDUCTOR STORAGE;

EID: 34250782123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251777     Document Type: Conference Paper

References (6)

1. D. S. Byeon, et al., "An 8Gb Multi-Level NAND Flash Memory with 63nm STI CMOS Process Technology," International Solid State Circuit Conference, 2.2, p. 46-47, 2005.
2. S.J. Lee, et al., "A 3.3V, 4Gb, four-level NAND Flash Memory with 0.09μm CMOS technology," ISSCC Digest of Technical Papers, pp. 52-53, Feb. 2004.
3. T. H. Cho, et al., "A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes," IEEE Journal of Solid-State Circuits Vol. 36, No. 11, pp. 1700-1706, Nov. 2001.
4. J. Lee, et al., "A 1.8V, 2Gb NAND Flash Memory for Mass Storage Applications," ISSCC Digest of Technical Papers, Vol 46, pp. 290-291, Feb. 2003.
5. T. Tanaka, et al., "A Quick intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3V-only NANA Flash Memory," IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, pp. 1149-1156, Nov. 1994.
6. K.D. Suh, et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," in ISCC Digest of Technical Papers, pp. 128-129, Feb. 1995.