Phase noise simulation and modeling of ADPLL by system verilog

BMAS 2008 - Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop

Volumn , Issue , 2008, Pages 29-34

  Wen, Tingjun ^a   Kwasniewski, Tad ^b  

^a Integrated Device Technology   (Canada)

^b CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNERS; CIRCUIT-LEVEL SIMULATIONS; EVENT-DRIVEN; EVENT-DRIVEN SIMULATIONS; F-PHASE; NOISE EFFECTS; PHASE NOISE SIMULATIONS; SIMPLE STOCHASTIC; VERILOG;

PHASE NOISE;

EID: 62449142552     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BMAS.2008.4751235     Document Type: Conference Paper

References (7)

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