Modeling and simulation to the design of la fractional-N frequency synthesizer

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 291-296

  Shuilong, Huang ^a   Huainan, Ma ^b   Zhihua, Wang ^a  

^a TSINGHUA UNIVERSITY   (China)

^b RFIC Corporation   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; COMPUTER HARDWARE DESCRIPTION LANGUAGES; MATHEMATICAL MODELS; NONLINEAR SYSTEMS; PHASE NOISE; VOLTAGE CONTROL;

NONLINEAR EFFECTS; VOLTAGE-DOMAIN VERILOGA/VERILOG MODELS;

COMPUTER AIDED DESIGN;

EID: 34548329589     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364606     Document Type: Conference Paper

References (5)

1. M. H. Perrot, M. D. Trott, and C.G. Sodini, A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis, IEEE J. Solid-State Circuits, 37, 8, 1028-1038, 2002.
2. Yiwu Tang and Mohammed Ismail, A methodology for fast SPICE simulation of frequency synthesizers, IEEE Circuits and Devices Mag., 16, 4, 10-15, 2000.
3. K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizer, Available from www.designers-guide.com, May, 2003.
4. Abhijit Phanse, Ramin Shirani, Behavioral modeling of a phase locked loop, Southcon/96, 400-404, 1996.
5. W. Rhee, B. S. Song and A. Al, A 1.1 -GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΣΔ modulator, IEEE J. Solid-State Circuits, 35, 10, 1453-1460, 2000.