A miniature stacked spiral inductor utilizing a proposed taper structure for RFIC size reduction

Proceedings of the 38th European Microwave Conference, EuMC 2008

Volumn , Issue , 2008, Pages 622-625

  Park, Sang Gyu ^a   Lee, Kwang Du ^a   Kim, Yusin ^a  

^a Samsung Electro Mechanics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC INDUCTORS; INTEGRATED CIRCUITS; MICROWAVES; Q FACTOR MEASUREMENT; RADIO; RADIO WAVES; SIZE DETERMINATION;

CMOS RF AMPLIFIERS; MEASUREMENT RESULTS; QUALITY FACTORS; RADIO FREQUENCY CMOS; RADIO FREQUENCY INTEGRATED CIRCUITS; SIZE REDUCTIONS; STACKED INDUCTORS; STACKED SPIRAL INDUCTORS; TAPER STRUCTURES;

CMOS INTEGRATED CIRCUITS;

EID: 62349086515     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUMC.2008.4751529     Document Type: Conference Paper

References (6)

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6. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RFIC's," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.