A CMOS VGA with DC offset cancellation for direct-conversion receivers

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 1, 2009, Pages 103-113

  Zheng, Yuanjin ^a   Yan, Jiangnan ^b   Xu, Yong Ping ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

dB linear variable gain amplifier (VGA); DB linear VGA; Dc offset; DC offset; Direct conversion receiver; Direct conversion receiver; I Q tuning; Pre distortion compensation

Indexed keywords

ANALOG CIRCUITS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; MILLIMETER WAVE DEVICES; RADIO RECEIVERS; TUNING; VOLTAGE REGULATORS;

DB-LINEAR VGA; DC OFFSETS; DIRECT CONVERSION RECEIVERS; LINEAR VARIABLE GAIN AMPLIFIERS; PRE-DISTORTION COMPENSATION;

VARIABLE GAIN AMPLIFIERS;

EID: 60749103576     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2010592     Document Type: Article

References (27)

1. B. Razavi, "Design considerations for direct-conversion receivers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 3, pp. 428-435, Mar. 1997.
2. R. Gomez and A. A. Abidi, "A 50 MHz variable gain amplifier cell in 2 μm CMOS," in Proc. IEEE Custom Integr. Circuits Conf., May 12-15, 1991, pp. 9.4/1-9.4/3.
3. F. Behbahani, A. Karimi, W. G. Tan, and A. Roithmeier, "Adaptive analog IF signal processor for a wideband CMOS wireless receiver," IEEE J. Solid-State Circuits vol. 36, no. 8, pp. 1205-1217, Aug. 2001.
4. V. Gopinathan, M. Tarsia, and D. Choi, "Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in sub-micrometer CMOS," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1698-1707, Dec. 1999.
5. Y. S. Youn and J. H. Choi, "A CMOS IF transceiver with 90 dB linear control VGA for IMT-2000 application," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2003, pp. 131-134.
6. A. Motamed, C. Hwang, and M. Ismail, "CMOS exponential current-to-voltage converter," Electron. Lett., vol. 33, pp. 998-1000, 1997.
7. S. Vlassis, "CMOS current-mode pseudo-exponential function circuit," Electron. Lett., vol. 37, pp. 471-472, 2001.
8. C. C. Cheng and S. I. Liu, "Pseudo-exponential function for MOSFETs in saturation," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 10, pp. 1318-1321, Oct. 2000.
9. L. Yu and W. M. Snelgrove, "A novel adaptive mismatch cancellation system for quadrature IF radio receivers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 789-801, Jun. 1999.
10. M. Valkama, M. Renfors, and V. Koivunen, "Advanced methods for I/Q imbalance compensation in communication receivers," IEEE Trans. Signal Process., vol. 49, no. 10, pp. 2335-2344, Oct. 2001.
11. J. K. Cavers and M. W. Liao, "Adaptive compensation for imbalance and offset losses in direct conversion transceivers," IEEE Trans. Veh. Technol., vol. 42, no. 6, pp. 581-588, Nov. 1993.
12. K. Itoh, M. Shimozawa, N. Suematsu, and O. Ishida, "Even harmonic type direct conversion receivers ICs for mobile handsets: Design challenges and solutions," in Proc. IEEE RFIC Symp., Jun. 1999, pp. 53-56.
13. A. Rofourgaran, G. Chane, J. J. Rael, Y. C. Chane, M. Rofourgaran, P. J. Chang, M. Djafari, M. K. Ku, E. W. Roth, A. A. Abidi, and H. Samucli, "A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS, II. Receiver design," IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 535-547, Apr. 1998.
14. K. Bult and H. Wallinga, "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation," IEEE J. Solid-State Circuits, vol. 22, no. 3, pp. 357-365, Jun. 1987.
15. E. Seevinck and R. F. Wassenaar, "A versatile CMOS linear transconductor/square-law function circuit," IEEE J. Solid-State Circuits, vol. 22, no. 3, pp. 366-377, Jun. 1987.
16. S.-Y. Hsiao and C.-Y. Wu, "A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer," IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 859-869, Jun. 1998.
17. B. Razavi, Design of Analog CMOS Integrator Circuits. New York: McGraw-Hill, 2001.
18. M. Schechter, Principles of Functional Analysis. Providence, RI: Amer. Math. Soc., 2001.
19. K.-Y. Lee, S.-W. Lee, Y. Koo, Y.-K. Huh, H.-Y. Nam, J.-W. Lee, J. Park, K. Lee, D.-K. Jeong, and W. Kim, "Full-CMOS 2-GHzWCDMA direct conversion transmitter and receiver," IEEE J. Solid-State Circuits vol. 38, no. 1, pp. 43-53, Jan. 2003.
20. T. Yamaji, N. Kanou, and T. Itakura, "A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 553-558, May 2002.
21. S. J. Yoo, A. Ravindran, and M. Ismail, "A low voltage CMOS transresistance based variable gain amplifier," in Proc. IEEE Int. Symp. Circuit Syst., 2004, vol. I, pp. 809-812.
22. J. K. Kwon, K. D. Kim, W. C. Song, and G. H. Cho, "Wideband high dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications," Electron. Lett., vol. 39, no. 10, pp. 759-760, Mar. 2003.
23. H. O. Elwan and M. Ismail, "Digitally programmable decibel-linear CMOS VGA for low-power mixed-signal applications," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 5, pp. 388-398, May 2000.
24. S. C. Tsou, C. F. Li, and P. C. Huang, "A low power CMOS linear-in-decibel variable gain amplifier with programmable bandwidth and stable group delay," IEEE Trans. Circuits Syst. II, Exp. Briefs vol. 53, no. 12, pp. 1436-1440, Dec. 2006.
25. F. Gatta, D. Manstretta, P. Rossi, and F. Svelto, "A fully integrated 0.18-μm CMOS direct conversion receiver front-end with on-chip LO for UMTs," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 15-23, Jan. 2004.
26. Q. H. Duong, Q. Le, C. W. Kim, and S. G. Lee, "A 95-dB linear low-power variable gain amplifier," IEEE Trans. Circuits Syst. I, Reg. Papers vol. 53, no. 8, pp. 1648-1656, Aug. 2006.
27. Z.-S. Cheng and J.-C. Bor, "A CMOS variable gain amplifier with DC offset calibration loop for wireless communications," in Proc. Int. Symp. VLSI Design, Autom. and Test, Apr. 2006, pp. 1-4.