CMOS-compatible zero-mask one time programmable (OTP) memory design

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 861-864

  Chan, Wan Tim ^a   Ng, K P ^a   Lee, M C ^a   Kwong, K C ^a   Li, N ^a   Ng, Ricky M Y ^a   Man, Tsz Yin ^a   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; CMOS-COMPATIBLE; HIGH BREAKDOWN VOLTAGES; MEMORY CELLS; MEMORY ELEMENTS; ONE-TIME PROGRAMMABLE MEMORIES; OPTIMAL COMBINATIONS; STANDARD CMOS PROCESS;

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; IONIZATION OF GASES;

DIODES;

EID: 60649106992     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734679     Document Type: Conference Paper

References (6)

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5. K. kato et. al., IEEE Transactions on Electron Devices, Volume 29, Issue 8, Aug 1982 pp. 1156-1161.
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