A fermi level controlled high voltage transistor preventing subthreshold hump

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 172-175

  Park, Byoung Chul ^a,b   Lee, Sung Young ^a,c   Chang, Dong Ryul ^a,b,c   Bang, Kee In ^b   Kim, Sung Jun ^b   Yi, Sang Bae ^b   Jung, Eun Seung ^b  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

^b SYSTEM LSI Division Semiconductor Business   (South Korea)

^c SAMSUNG Electronics   (South Korea)

Author keywords

Boron segregation; FCHVT; High voltage; Hump; HV; STI

Indexed keywords

BORON SEGREGATION; FCHVT; HIGH VOLTAGE; HUMP; HV; STI;

BORON; BORON COMPOUNDS; ELECTRICITY; FERMI LEVEL; FERMIONS; INTEGRATED CIRCUITS; SEGREGATION (METALLOGRAPHY); SEMICONDUCTING SILICON; SPEECH ANALYSIS;

DC GENERATORS;

EID: 60649090491     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734501     Document Type: Conference Paper

References (5)

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2. W. G. Kim, et al., "New Corner Rounding Process for Sub-O.l5μ Shallow Trench Isolation", IEEE, 1999, pp. 133-135
3. J. Y. Lee, "Novel Cell Transistor Using Retracted Si3N4-liner STI for the Improvement of Data Retention Time in Gigabit Density DRAM and Beyond", IEEE, vol. 48, June 2001, pp. 1152-1158
4. P. Dimitrakis, "Parasitic memory effects in shallow-trench- isolated nanocrystal memory devices", Solid-State Electronics, 51, (2007),pp 147-158
5. Cheolho Baek "Data Retention Time and Cell Transistor Improvement in Dual Gate Oxide Scheme for Giga Bit DRAM Era"