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Volumn 5, Issue , 2008, Pages 353-357

Heterogeneous multi-core design for information retrieval efficiency on the vector space model

Author keywords

[No Author keywords available]

Indexed keywords

BASIC OPERATIONS; CORE DESIGNS; DATA PATTERNS; HARDWARE IMPLEMENTATIONS; INPUT DATUMS; INTELLECTUAL PROPERTIES CORES; MEMORY SYSTEMS; MULTI-CORE SYSTEMS; OVERALL EFFICIENCIES; SPEED-UP; VECTOR SPACE MODELS;

EID: 58149132135     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FSKD.2008.229     Document Type: Conference Paper
Times cited : (1)

References (12)
  • 1
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    • Scholer, F.1    Williams, H.E.2    Yiannis, J.3    Zobel, J.4
  • 2
    • 0036993118 scopus 로고    scopus 로고
    • B. Pssas, N. Ziviani, W. M. Jr., and B. Ribeiro-Neto, Set-based model: A new approach for information retrieval, SIGIR 2002, pp. 2300-237.
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  • 3
    • 0003214715 scopus 로고    scopus 로고
    • Evaluating the performance of distributed architectures for information retrieval using a variety of workloads
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    • (2000) ACM Transactions on Information Systems , vol.18 , Issue.1 , pp. 1-43
    • Cahoon, B.1    Mckinley, K.S.2
  • 4
    • 33750351831 scopus 로고    scopus 로고
    • Load balancing for term-distributed parallel retrieval
    • A. Moffat, W. Webber, and J. Zobel, "Load balancing for term-distributed parallel retrieval", SIGIR 2006, pp. 348-355.
    • (2006) SIGIR , pp. 348-355
    • Moffat, A.1    Webber, W.2    Zobel, J.3
  • 6
    • 0031235242 scopus 로고    scopus 로고
    • H. Lance, B. A. N., and O. Kunle, A single-chip multiprocessor, Computer, 30, no. 9, 1997, pp. 79-85.
    • H. Lance, B. A. N., and O. Kunle, "A single-chip multiprocessor", Computer, vol. 30, no. 9, 1997, pp. 79-85.
  • 7
    • 0035104225 scopus 로고    scopus 로고
    • Architecture of the atlas chip-multiprocessor: Dynamically parallelizing irregular applications
    • L. Codrescu, D. Wills, and J. Meindl, "Architecture of the atlas chip-multiprocessor: dynamically parallelizing irregular applications", IEEE Tran. Comput., vol. 50, no. 1, 2001, pp. 67-82.
    • (2001) IEEE Tran. Comput , vol.50 , Issue.1 , pp. 67-82
    • Codrescu, L.1    Wills, D.2    Meindl, J.3
  • 9
    • 85008065233 scopus 로고    scopus 로고
    • Processor power reduction via single-isa heterogeneous multi-core architectures
    • R. Kumar, K. I. Farkas, and N. P. Jouppi, "Processor power reduction via single-isa heterogeneous multi-core architectures", Computer Architecture Letters, vol. 2, 2003.
    • (2003) Computer Architecture Letters , vol.2
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  • 10
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    • An fpga implementation and performance evaluation of the serpent block cipher
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  • 11
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    • Computer evaluation of indexing and text processing
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    • Salton, G.1    Lesk, M.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.