Nano-scaled functional layers for current and heat transport in electronics packaging

Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC

Volumn , Issue , 2008, Pages 333-338

  Heimann, Matthias ^a   Meißner, Frank ^b   Schönecker, Andreas ^b   Endler, Ingolf ^b   Wolter, Klaus Jürgen ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b FRAUNHOFER INSTITUTE FOR CERAMIC TECHNOLOGIES AND SYSTEMS   (Germany)

Author keywords

Aligned; Carbon nanotubes; Chip cooling; CNT; CVD; Heat sink; Substrate

Indexed keywords

BRAZING; CARBON NANOTUBES; CATALYSIS; CHEMICAL VAPOR DEPOSITION; CHIP SCALE PACKAGES; COOLING; ELECTRIC PROPERTIES; ELECTRONICS INDUSTRY; ELECTRONICS PACKAGING; FILM PREPARATION; HEAT SINKS; INTEGRATED CIRCUITS; JOINING; LEAD; MECHANICAL PROPERTIES; NANOCOMPOSITES; NANOSTRUCTURED MATERIALS; NANOTUBES; PACKAGING MATERIALS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; SOLDERING; SOLDERING ALLOYS; SUBSTRATES; WELDING;

ALIGNED; AMOUNT OF INFORMATIONS; ART METHODS; ASSEMBLY MECHANISMS; BOTTOM-UP; CATALYST LAYERS; CHEMICAL VAPOUR DEPOSITIONS; CHIP COOLING; CNT; CNT FILMS; COMMON MATERIALS; COMPUTER CHIPS; CONDUCTING LAYERS; CONDUCTING MATERIALS; CVD; DIE BONDINGS; DISSIPATION LOSSES; DOWNSCALING; ELECTRICAL PROPERTIES; ELECTRICAL TRANSPORTS; ELECTRONIC DEVICES; ELEMENT MATERIALS; FATIGUE RESISTANCES; FUNCTIONAL LAYERS; FUNCTIONAL PROPERTIES; FUTURE APPLICATIONS; HEAT TRANSPORTS; HIGH DENSITIES; HIGH FREQUENCIES; INTERCONNECT MATERIALS; JOINING MATERIALS; LEAD-FREE SOLDERS; MICROELECTRONIC INDUSTRIES; MINIATURISATION; NANOMETRE SCALES; PACKAGING SUBSTRATES; PHYSICAL BARRIERS; RELIABILITY REQUIREMENTS; REPRODUCIBILITY; SI SURFACES; SOLDER BUMPS; THERMO MECHANICALS; WALL STRUCTURES;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 58149098320     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2008.4684371     Document Type: Conference Paper

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