Reduction of low-frequency noise in MOSFETs under switched gate and substrate bias

ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Volumn , Issue , 2008, Pages 266-269

  Šiprak, Domagoj ^a   Zanolla, Nicola ^a,b   Tiebout, Marc ^c   Baumgartner, Peter ^a   Fiegna, Claudio ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; MOSFET DEVICES; THERMAL NOISE;

BIASING SCHEMES; CMOS CIRCUITS; EMISSION TIME CONSTANTS; GATE BIASES; LOW-FREQUENCY NOISES; MOS FETS; SUBSTRATE BIASES;

SUBSTRATES;

EID: 58149092692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681749     Document Type: Conference Paper

References (8)

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7. T. Schiml et. al. , "A 0.13um CMOS Platform with Cu/Low-k Interconnects for System On Chip Applications," VLSI 2001, pp. 101-102.
8. J.S. Kolhatkar, C. Salm, M.J. Knitel, and H. Wallinga, "Constant and Switched Bias Low Frequency Noise in p-MOSFETs with VaryingGate Oxide Thickness," Proc. ESSDERC 2002, pp. 83-86, 2002.