메뉴 건너뛰기




Volumn , Issue , 2008, Pages 189-192

A 1.33 Gsps 5-bit 2 stage pipelined flash analog to digital converter for UWB targeting 8 stage time interleaving architecture

Author keywords

ADC; Flash; Pipeline; Time interleaving; UWB

Indexed keywords

ANALOG TO DIGITAL CONVERSION; ARCHITECTURE; ARSENIC; BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MICROSYSTEMS; NANOELECTRONICS; PIPELINES; SPEED; TELECOMMUNICATION SYSTEMS;

EID: 58049185475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MNRC.2008.4683410     Document Type: Conference Paper
Times cited : (2)

References (9)
  • 1
    • 58049156976 scopus 로고    scopus 로고
    • I-Hsin Wang and Shen-luan Liu, A 1 V 5 bit 5 Gsample/sec CMOS ADC for UWB Receivers, IEEE Transactions 2007.
    • I-Hsin Wang and Shen-luan Liu, "A 1 V 5 bit 5 Gsample/sec CMOS ADC for UWB Receivers", IEEE Transactions 2007.
  • 6
    • 58049175597 scopus 로고    scopus 로고
    • Design of Sample-and-Hold amplifiers for High-Speed Low-Voltage A/D Converters
    • Behzad Razavi, "Design of Sample-and-Hold amplifiers for High-Speed Low-Voltage A/D Converters", IEEE 1997
    • (1997) IEEE
    • Razavi, B.1
  • 7
    • 22544471871 scopus 로고    scopus 로고
    • Christopher Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner: A 6 bit. 1.2 GSPS Low-Power Flash-ADC in 0.13um Digital CMOS, IEEE 2005.
    • Christopher Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner: "A 6 bit. 1.2 GSPS Low-Power Flash-ADC in 0.13um Digital CMOS", IEEE 2005.
  • 8
    • 58049187976 scopus 로고    scopus 로고
    • www.wikipedia.org
  • 9
    • 58049147371 scopus 로고    scopus 로고
    • Fat tree encoder design for ultra-high speed flash A/D converters
    • Daegyu Lee, Jinchoel Yoo, Kyusun Choi, and Jahan Ghaznavi: "Fat tree encoder design for ultra-high speed flash A/D converters", IEEE 2002.
    • IEEE 2002
    • Lee, D.1    Yoo, J.2    Choi, K.3    Ghaznavi, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.