A 1.33 Gsps 5-bit 2 stage pipelined flash analog to digital converter for UWB targeting 8 stage time interleaving architecture

1st Microsystems and Nanoelectronics Research Conference, MNRC 2008 - Enabling Synergy and Accelerating Excellence in Graduate Student Research

Volumn , Issue , 2008, Pages 189-192

  Sivakumar, Balasubramanian ^a   Rajaraman, Athreya Vydhyanathan ^a   Ismail, Mohammed ^a  

^a OHIO STATE UNIVERSITY   (United States)

Author keywords

ADC; Flash; Pipeline; Time interleaving; UWB

Indexed keywords

ANALOG TO DIGITAL CONVERSION; ARCHITECTURE; ARSENIC; BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MICROSYSTEMS; NANOELECTRONICS; PIPELINES; SPEED; TELECOMMUNICATION SYSTEMS;

ADC; ADC ARCHITECTURES; AT SPEEDS; CENTER FREQUENCIES; CMOS PROCESSES; CMOS TECHNOLOGIES; CURRENT TRENDS; DIGITAL DOMAINS; DIGITAL PARTS; DUTY CYCLES; FLASH; FLASH ANALOG TO DIGITAL CONVERTERS; FRONT ENDS; HIGH POWERS; HIGH RESOLUTIONS; HIGH SPEEDS; INPUT FREQUENCIES; INTEGRABILITY; INTERLEAVING ARCHITECTURES; LOW POWERS; LOW VOLTAGE SUPPLIES; POWER SUPPLIES; RECEIVER ARCHITECTURES; TIME INTERLEAVING; TIME-INTERLEAVED; UWB; WIRELESS COMMUNICATIONS;

MULTICARRIER MODULATION;

EID: 58049185475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MNRC.2008.4683410     Document Type: Conference Paper

References (9)

1. I-Hsin Wang and Shen-luan Liu, "A 1 V 5 bit 5 Gsample/sec CMOS ADC for UWB Receivers", IEEE Transactions 2007.
2. W. Cheng, W. Ali, M. Choi, K. Liu, T. Tat, D. Devendorf, L.Linder, and R. Stevens, "A 3b 40GS/s ADC-DAC in 0.12ptm SiGe" IEEE International Solid-State Circuits Conference, pp. 262-263, Feb. 2004
3. Franco Maloberti, Data Converters, 2007
4. N. Weste and D. Harris, CMOS VLSI Design A Circuits and Systems Perspective, 3rd Edition
5. Behzad Razavi, Principles of Data Conversion System Design. 1995
6. Behzad Razavi, "Design of Sample-and-Hold amplifiers for High-Speed Low-Voltage A/D Converters", IEEE 1997
7. Christopher Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner: "A 6 bit. 1.2 GSPS Low-Power Flash-ADC in 0.13um Digital CMOS", IEEE 2005.
8. www.wikipedia.org
9. Daegyu Lee, Jinchoel Yoo, Kyusun Choi, and Jahan Ghaznavi: "Fat tree encoder design for ultra-high speed flash A/D converters", IEEE 2002.