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Volumn , Issue , 2008, Pages 189-192
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A 1.33 Gsps 5-bit 2 stage pipelined flash analog to digital converter for UWB targeting 8 stage time interleaving architecture
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Author keywords
ADC; Flash; Pipeline; Time interleaving; UWB
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Indexed keywords
ANALOG TO DIGITAL CONVERSION;
ARCHITECTURE;
ARSENIC;
BANDWIDTH;
CMOS INTEGRATED CIRCUITS;
ELECTRIC POWER UTILIZATION;
MICROSYSTEMS;
NANOELECTRONICS;
PIPELINES;
SPEED;
TELECOMMUNICATION SYSTEMS;
ADC;
ADC ARCHITECTURES;
AT SPEEDS;
CENTER FREQUENCIES;
CMOS PROCESSES;
CMOS TECHNOLOGIES;
CURRENT TRENDS;
DIGITAL DOMAINS;
DIGITAL PARTS;
DUTY CYCLES;
FLASH;
FLASH ANALOG TO DIGITAL CONVERTERS;
FRONT ENDS;
HIGH POWERS;
HIGH RESOLUTIONS;
HIGH SPEEDS;
INPUT FREQUENCIES;
INTEGRABILITY;
INTERLEAVING ARCHITECTURES;
LOW POWERS;
LOW VOLTAGE SUPPLIES;
POWER SUPPLIES;
RECEIVER ARCHITECTURES;
TIME INTERLEAVING;
TIME-INTERLEAVED;
UWB;
WIRELESS COMMUNICATIONS;
MULTICARRIER MODULATION;
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EID: 58049185475
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/MNRC.2008.4683410 Document Type: Conference Paper |
Times cited : (2)
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References (9)
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