A power-efficient impoved-stability 6T SRAM cell in 45nm multi-channel FET technology

ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Volumn , Issue , 2008, Pages 150-153

  Thomas, Olivier ^a   Guillaumot, Bernard ^b   Ernst, Thomas ^a   Cousin, Bastien ^a   Rozeau, Olivier ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; MESFET DEVICES; THREE DIMENSIONAL;

6T-SRAM; CELL STABILITIES; ELECTRICAL RESULTS; POWER DISSIPATIONS; READ ACCESS TIMES; SIMULATION MODELS;

STATIC RANDOM ACCESS STORAGE;

EID: 58049116109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681721     Document Type: Conference Paper

References (7)

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4. M. Kim, et al, "122 Mb High Speed SRAM Cell with 25 nm Gate Length Multi-Bridge-Channel MOSFET (MBCFET) on Bulk Si Substrate", VLSI Tech Dig, 2006
5. L. Chang, et al., "Stable SRAM Cell Design for the 32 nm Node and Beyond", VLSI Tech Dig., 2005
6. O. Thomas, et at, "Sub-lV, Robust and Compact 6T SRAM cell in Double GateMOS technology", ISCAS 2007
7. M. Reyboz, et al., "Explicit Threshold Voltage Based Compact Model of Independent Double Gate MOSFET", WCM, 2006