Suppression of power/ground noise using differential vias

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2008, Pages 325-328

  Chen, Ruiming ^a   Wang, Haining ^a   Abhari, Ramesh ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; NOISE POLLUTION;

CAVITY METHODS; FULLWAVE SIMULATIONS; IN COMPONENTS; NOISE MAPS; PIN ASSIGNMENTS; REFERENCE VOLTAGES;

ELECTRONICS PACKAGING;

EID: 58049097612     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675946     Document Type: Conference Paper

References (7)

1. R. Abhari, and G. V. Eleftheriades, "Metallio-Dielectric electromagnetic band-gap structures for suppression and isolation of the parallel-plate noise in high-speed circuits," IEEE Trans. Microwave Theory and Techniques, vol. 51, June 2003, pp. 1629-1639.
2. R. Abhari, G. V. Eleftheriades, and E. van Deventer-Perkins, "Physics-based CAD models for the analysis of vias in parallel-plate environments," IEEE Trans. Microwave Theory and Techniques, vol. 49, Oct. 2001, pp. 1697-1707.
3. th Electronic Components and Technology Conference, 1995, pp. 361-367.
4. C. Schuster, G. Selli, Y. H. Kwark, M. B. Ritter, and J. L. Drewniak, "Progress in representation and validation of physics-based via models," IEEE Workshop on Signal Propagation on Interconnects, SPI 2007,May 2007, pp. 145-148.
5. Z. L. Wang, O. Wada, Y. Toyota, and R. Koga, "Convergence acceleration and accuracy improvement in power bus impedance calculation with a fast algorithm using cavity modes," IEEE Trans. Electromagnetic Compatibility ,vol. 47, Feb. 2005, pp. 2-9.
6. G. T. Lei, R. W. Techentin, and B. K. Gilbert, "High-frequency characterization of power/ground-plane structures," IEEE Trans. Microwave Theory and Techniques, vol. 47, May 1999, pp. 562-569.
7. C. Wang, J. Mao, G. Selli, S. Luan, L. Zhang, J. Fan, D. J. Pommerenke, R. E. DuBroff, and J. L. Drewniak, "An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances," IEEE Trans. Advanced Packaging, vol. 29, May 2006, pp. 320-334.