An efficient method for simulation of multiple catastrophic faults

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 356-359

  Tadeusiewicz, Michał ^a   Hałgas, Stanisław ^a  

^a LODZ UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Analogue circuits; Fault simulations; Multiple catastrophic faults

Indexed keywords

ANALOGUE CIRCUITS; COMPUTING POWERS; EFFICIENT METHODS; FAULT SIMULATIONS; FAULTY ELEMENTS; MULTIPLE CATASTROPHIC FAULTS; NODE IMPEDANCE MATRIXES; NUMERICAL EXAMPLES; OPEN CIRCUITS; SHORT CIRCUITS; SYSTEMATIC METHODS;

NETWORKS (CIRCUITS);

EID: 57849157095     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674864     Document Type: Conference Paper

References (17)

1. C. Alippi, M. Catelani, A. Fort, R. Singuaroli, I. Trotta, "An embedded automatic SBT diagnosis system for analog circuits", Proc. 21st IEEE Instrumentation and Measurement Technology Conference, IMTC 04, vol. 3, 2156-2160, 2004.
2. F. Aminian, M. Aminian, "Fault diagnosis of analog circuits using bayesian neural networks with wavelet transform as preprocessor", Journal of Electronic Testing, vol. 17, 29-36, 2001.
3. M. Tadeusiewicz, M. Korzybski, "A method for fault diagnosis in linear electronic circuits", Int. Cir. Theor. Appl., 28, 245-262, 2000.
4. D. Liu, J.A. Starzyk, "A. generalized fault diagnosis in dynamic analog circuits", Int. J. Cir. Theor Appl., vol. 30, 487-510, 2002.
5. M. Tadeusiewicz, S Hałgas, M. Korzybski, "An algorithm for soft fault diagnosis of linear and nonlinear circuits", IEEE Trans. Cir. Syst. -I: Fundamental Theory and Applications, vol. 49, 1648-1653, 2002.
6. M. Worsman, M. Wong, Y. Lee, "Enhancing the fault diagnosis of linear analog circuit steady-state DC testing through the analysis of equivalent faults", IEEE Trans. Cir. Sys. I: Fundamental Theory and Applications, vol. 50, 932-936, 2003.
7. M. Tadeusiewicz, S. Haigas, "An algorithm for multiple fault diagnosis in analogue circuits", Int. J, Cir. Theor, Appl., vol. 34, 607-615, 2006.
8. V.C. Prasad, N.S.C. Babu, "Selection of test nodes for analog fault diagnosis in dictionary approach", IEEE Trans. Instrum, Meas., vol. 49, 1289-1297, 2000.
9. J.A. Starzyk, D. Liu, Z. Liu, D.E. Nelson, J. Rutkowski, "Entropy-based optimum test points selection for analog fault dictionary techniques", IEEE Trans. Instrum. Meas., vol. 53, 754-761, 2004.
10. C. Alippi, M. Catelani, A. Fort, M. Mugnaini, "Automated selection of test frequencies for fault diagnosis in analog electronic circuits", IEEE Tran. Instrum. Meas., vol. 54, 1033-1044, 2005.
11. R. Shi, M. Tian, G. Shi, "Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation", IEEE Tran. on CAD of Integrated Circuits and Systems, vol. 25, 1392-1400, 2006.
12. A. Pahwa, R.A. Rohrer, "Band faults: efficient approximations to fault bands for the simulation before fault diagnosis of linear circuits", IEEE Trans. Circ. Syst., vol. 29, 81-88, 1982.
13. K.H. Leung, R. Spence, "Multiparameter large-change sensitivity analysis and systematic exploration", IEEE Trans. Cir. Syst., vol. 22, 796-804, 1975.
14. G.C. Temes, "Efficient methods of fault simulation", Proc. 20th Midwest Symposium on Circuits and Systems, 191-194, 1977.
15. A.S. Householder, The theory of matrices in numerical analysis, Blaisedell Publishing Company, New York, 1965.
16. L.O. Chua, P.M. Lin, Computer-aided analysis of electronic circuits: Algorithms and computational techniques, Prentice-Hall, Englewood Cliffs, N.J., 1975.
17. M. Tadeusiewicz, N. Assi, G. Ciesielski, "An algorithm for generation of the nodal impedance matrix for networks containing mutually coupled inductors", Int. J. El. Pow. Ener. Syst., 10, 36-40, 1988.