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Volumn , Issue , 2008, Pages 32-37

To SAT or not to SAT: Ashenhurst decomposition in a large scale

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

EID: 57849143788     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681548     Document Type: Conference Paper
Times cited : (22)

References (16)
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    • Ashenhurst, R.L.1
  • 3
    • 0035440923 scopus 로고    scopus 로고
    • Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping
    • J. Cong and Y.-Y. Hwang. Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 20(9):1077-1090, 2001.
    • (2001) IEEE Transactions on Computer-Aided Design of Integrated Circuits , vol.20 , Issue.9 , pp. 1077-1090
    • Cong, J.1    Hwang, Y.-Y.2
  • 4
    • 0001663802 scopus 로고
    • Linear reasoning: A new form of the Herbrand-Gentzen theorem
    • W. Craig. Linear reasoning: A new form of the Herbrand-Gentzen theorem. J. Symbolic Logic, 22(3):250-268, 1957.
    • (1957) J. Symbolic Logic , vol.22 , Issue.3 , pp. 250-268
    • Craig, W.1
  • 6
    • 21444441175 scopus 로고    scopus 로고
    • An extensible SAT-solver
    • N. Eén and N. Söensson. An extensible SAT-solver. In Proc. SAT, pp.502-518, 2003.
    • (2003) Proc. SAT , pp. 502-518
    • Eén, N.1    Söensson, N.2
  • 7
    • 35048820104 scopus 로고    scopus 로고
    • Functional dependency for verification reduction
    • J.-H. R. Jiang and R. K. Brayton. Functional dependency for verification reduction. In Proc. CAV, pp.268-280, 2004.
    • (2004) Proc. CAV , pp. 268-280
    • Jiang, J.-H.R.1    Brayton, R.K.2
  • 8
    • 0031635672 scopus 로고    scopus 로고
    • Compatible class encoding in hyper-function decomposition for FPGA synthesis
    • J.-H. R. Jiang, J.-Y. Jon, and J.-D. Huang. Compatible class encoding in hyper-function decomposition for FPGA synthesis. In Proc. DAC, pp.712-717, 1998.
    • (1998) Proc. DAC , pp. 712-717
    • Jiang, J.-H.R.1    Jon, J.-Y.2    Huang, J.-D.3
  • 9
    • 0001287225 scopus 로고
    • Functional decomposition and switching circuit design
    • 11(2):291V335
    • R. M. Karp. Functional decomposition and switching circuit design. J. Soc. Ind. Appl. Math. 11(2):291V335, 1963.
    • (1963) J. Soc. Ind. Appl. Math
    • Karp, R.M.1
  • 10
    • 50249153650 scopus 로고    scopus 로고
    • Scalable exploration of functional dependency by interpolation and incremental SAT solving
    • C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko. Scalable exploration of functional dependency by interpolation and incremental SAT solving. In Proc. ICCAD, pp.227-233, 2007.
    • (2007) Proc. ICCAD , pp. 227-233
    • Lee, C.-C.1    Jiang, J.-H.R.2    Huang, C.-Y.3    Mishchenko, A.4
  • 11
    • 51549096990 scopus 로고    scopus 로고
    • Bi-decomposing large Boolean functions via interpolation and satisfiability solving
    • R.-R. Lee, J.-H. R. Jiang, and W.-L. Hung. Bi-decomposing large Boolean functions via interpolation and satisfiability solving. In Proc. DAC, 2008.
    • (2008) Proc. DAC
    • Lee, R.-R.1    Jiang, J.-H.R.2    Hung, W.-L.3
  • 12
    • 27944492443 scopus 로고    scopus 로고
    • FPGA technology mapping: A study of optimally. In Proc
    • A. Ling, D. Singh, and S. Brown. FPGA technology mapping: A study of optimally. In Proc. DAC, pp.427-432, 2005.
    • (2005) DAC , pp. 427-432
    • Ling, A.1    Singh, D.2    Brown, S.3
  • 13
    • 33745162025 scopus 로고    scopus 로고
    • Interpolation and SAT-based model checking
    • K. L. McMillan. Interpolation and SAT-based model checking. In Proc. CAV, pp.1-13, 2003.
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    • McMillan, K.L.1
  • 16
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    • Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs
    • B. Wurth, U. Schlichtmann, K. Eckl, and K. Antreich. Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. ACM Trans. on Design Automation of Electronic Systems, 4(3):313-350, 1999.
    • (1999) ACM Trans. on Design Automation of Electronic Systems , vol.4 , Issue.3 , pp. 313-350
    • Wurth, B.1    Schlichtmann, U.2    Eckl, K.3    Antreich, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.