Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 712-717

  Jiang, Jie Hong R ^a   Jou, Jing Yang ^a   Huang, Juinn Dar ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ENCODING (SYMBOLS); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE ENHANCEMENT; ALGORITHMS; PROBLEM SOLVING;

DECOMPOSABILITY; ENCODING ALGORITHMS; ENCODING METHODS; FPGA TECHNOLOGY; FUNCTIONAL DECOMPOSITION; MULTIPLE OUTPUTS; MULTIPLE-OUTPUT FUNCTION; SUB-EXPRESSIONS;

SIGNAL ENCODING; FIELD PROGRAMMABLE GATE ARRAYS;

MULTIPLE-OUTPUT FUNCTION;

EID: 0031635672     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Wen-Zen Shen, Juinn-Dar Huang and Shih-Min Chao, "Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping, " Proc. 32nd DAC, pp.65-69, June 1995.
2. Jie-Hong Jiang, Jing-Yang Jou, Juinn-Dar Huang and Jung-Shang Wei, "BDD Based Lambda Set Selection in Roth-Karp Decomposition for LUT Architecture, " Proc. ASP-DAC, pp.259-264, January 1997.
3. Rajeev Murgai, Robert K. Brayton and Alberto Sangiovanni-Vincentelli, "Optimum Functional Decomposition Using Encoding, " Proc. 31" DAC, pp.408-414, June 1994.
4. Yung-Te Lai, Kuo-Rueih Ricky Pan and Massoud Pedram, "OBDD-Based Function Decomposition: Algorithms and Implementation, " IEEE Trans. CAD, vol. 15, pp.977-990, August 1996.
5. Bemd Wurth, Klaus Eckl and Kurt Antreich, "Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm, " Proc. 32 DAC, pp.54-59, June 1995.
6. Juinn-Dar Huang, Jing-Yang Jou and Wen-Zen Shen, "Compatible Class Encoding in Roth-Karp Decomposition for Two-Output LUT Architecture, " Proc. Intl. Conf. on CAD, pp.359-363, Nov. 1995.
7. Christian Legl, Bernd Wurth and Klaus Eckl, "An Implicit Algorithm for Support Minimization during Functional Decomposition, " Proc. European Design and Test Conf., 1996.
8. Hiroshi Sawada, Takayuki Suyama and Akira Nagoya, "Logic Synthesis for Look-Up Table based FPGAs using Functional Decomposition and Support Minimization, " Proc. Intl. Conf. on CAD, pp.353358, Nov. 1995.
9. Daniel D. Gajski, Nikil D. Dutt, Allen C-H Wu and Steve Y-L Lin, High-Level Synthesis, Kluwer Ac. Pub., 1992.
10. Randal E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation, " IEEE Trans, on Computers, pp.677-691, August 1986.
11. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and A. R. Wang, "MIS: A Multiple-Level Logic Optimization System, " IEEE Trans, on CAD, pp.1062-1081, Nov. 1987.
12. G. L. Nemhauser and L. A. Wolsey, Integer and Combinatorial Optimization, John Wiley, New York, 1988.
13. R. L. Ashenhurt, "The Decomposition of Switching Functions, " Ann. Computation Lab. of Harvard Univ., vol.29, pp.74-116, 1959.
14. J. P. Roth and R. M. Karp, "Minimization Over Boolean Graphs, " IBM Journal, pp.227-238, 1962.