An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 554-557

  Nasalski, Piotr ^a   Makosiej, Adam ^a   Giraud, Bastien ^b   Vladimirescu, Andrei ^b,c   Amara, Amara ^b  

^a LODZ UNIVERSITY OF TECHNOLOGY   (Poland)

^b Institut Superieur d'Electronique de Paris ISEP   (France)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); LEAKAGE CURRENTS; MOSFET DEVICES; NETWORKS (CIRCUITS); TRANSISTORS;

BACK GATES; FULLY DEPLETED; INPUT NODES; OPERATION MARGINS; PROCESS VARIATIONS; PROPOSED ARCHITECTURES; SELF-ALIGNED; SILICON ON INSULATORS; TRANSISTOR MISMATCHES; VOLTAGE SENSES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 57849118059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674913     Document Type: Conference Paper

References (5)

1. Kiyoo Itoh, and Riichiro Takemura, "Low-Voltage Limitations of Nano-Scale CMOS LSIs: Current Status and Future Trends", EDSSC, December 2007, Taiwan.
2. Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, and Kaushik Roy, "Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure", ISSCC, february 2007 San Francisco, CA, USA
3. Saibal Mukhopadhyay, Hamid Mahmoodi, and Kaushik Roy, "Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET", ISQED, March 2005, San Jose, CA, USA.
4. Hong-Yi Huang, and Shih-Lun Chen, "Self-isolated gain-enhanced sense amplifier", ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference, pp. 57-60
5. Bastien Giraud and Amara Amara, "Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS", DELTA, January 2008, Hong Kong.