Read stability and write ability tradeoff for 6T SRAM cells in double-gate CMOS

Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008

Volumn , Issue , 2008, Pages 201-204

  Giraud, Bastien ^a   Amara, Amara ^a  

^a Institut Superieur d'Electronique de Paris ISEP   (France)

Author keywords

Double gate (DG); SRAM cell; Static noise margin (SNM); Write margin (WM)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; CYTOLOGY; DRAIN CURRENT; ELECTRONICS ENGINEERING; MOSFET DEVICES; SILICON; STATIC RANDOM ACCESS STORAGE; TECHNICAL PRESENTATIONS;

DOUBLE GATE (DG); INTERNATIONAL SYMPOSIUM; SRAM CELL; STATIC NOISE MARGIN (SNM); WRITE MARGIN (WM);

SILICON ON INSULATOR TECHNOLOGY;

EID: 50649105048     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2008.98     Document Type: Conference Paper

References (4)

1. M. Yamaoka, K. Osada, R. Tsuchiya, M. Horiuchi, S. Kimura and T. Kawahara., "Low power SRAM menu for SOC application using yin-yang-feedback memory cell technology", Symp. VLSI Circuits Dig. 18, 2004.
2. A. Carlson, Z. Guo, S. Balasubramanian, L.-T. Pang, T.-J. King Liu, and B. Nikolic, "FinFET SRAM with Enhanced Read / Write Margins", SOI Conference, 2006.
3. O. Thomas, M. Reyboz and M. Belleville, "Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology", ISCAS 2007, New Orleans, USA.
4. M. Reyboz, T. Poiroux, O. Rozeau, P. Martin and J. Jomaah, "Explicit threshold voltage based compact model of independent double gate (IDG) MOSFET including short channel effects", CEA, Grenoble, France.