A power-efficient capacitor structure for high-speed charge recycling SAR ADCs

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 642-645

  Zhu, Yan ^a   Chio, U Fat ^a   Wei, He Gong ^a   Sin, Sai Weng ^a   Upa, Seng Pan ^a,b   Martins, R P ^a,c  

^a UNIVERSITY OF MACAU   (Macao)

^b Chipidea Microelectronics Ltd   (Macao)

^c INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS ENGINEERING; ELECTRONICS INDUSTRY;

BEHAVIORAL SIMULATION; CAPACITOR ARRAYS; CAPACITOR STRUCTURES; CHARGE RECYCLING; CIRCUIT'S PERFORMANCE; PARASITIC EFFECT; POWER EFFICIENT; SUCCESSIVE APPROXIMATION REGISTER;

RECYCLING;

EID: 57849085876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674935     Document Type: Conference Paper

References (5)

1. B. P. Ginsburg and A. P. Chandrakasan,"500-MS/s 5-bit ADC in 65nm CMOS with Split Capacitor Array DAC" IEEE J. Solid-State Circuits, vol.42, no.4, pp.739-746, Apr. 2007.
2. D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm. CMOS," ISSCC Dig. Tech. Papers, pp.264-265, Feb. 2004.
3. B.P.Ginsburg and A.P.Chandrakasan, "An. Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC," in Proc. IEEE ISCAS, pp. 184-187, May 2005.
4. M. S. W. Chen, and R. W. Brodersen, "A 6b 600 MS/s 5.3m.W asynchronous ADC in 0.13μm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 574-575, Feb. 2006.
5. G. Yin, F. Eynde, and W. Sanson, "A. High-Speed CMOS Comparator with 8-b Resolution," IEEE J. Solid-State Circuits, vol.27, no.2, pp.208-211, Feb. 1992.