Improving behavioral IO buffer modeling based on IBIS

IEEE Transactions on Advanced Packaging

Volumn 31, Issue 4, 2008, Pages 711-721

  Varma, Ambrish K ^a,b   Steer, Michael ^b   Franzon, Paul D ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b North Carolina State University   (United States)

Author keywords

Behavioral modeling; Gate modulation effect; Input output buffer information specification (IBIS); Input output (IO) Buffer modeling; Simultaneous switching noise (SSN)

Indexed keywords

AUTOMOBILE DRIVERS; INTEGRATED CIRCUITS; JITTER; MODULATION; SANITARY SEWERS; SEMICONDUCTOR QUANTUM DOTS; SWITCHING; TRANSISTORS;

BEHAVIORAL MODELING; GATE MODULATION EFFECT; INPUT OUTPUT BUFFER INFORMATION SPECIFICATION (IBIS); INPUT/OUTPUT (IO) BUFFER MODELING; SIMULTANEOUS SWITCHING NOISE (SSN);

SPECIFICATIONS;

EID: 57749115689     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2008.2004995     Document Type: Conference Paper

References (11)

1. A. Varma, M. Steer, and P. Franzon, "SSN issues with IBIS models," in IEEE 13th Topical Meeting Electrical Performance Electron. Packag. 2004, pp. 87-90.
2. Z. Yang, S. Huq, V. Arumugham, and I. Park, "Enhancement of IBIS modeling capability in simutanous switching noise (SSN) and other power integrity related simulations-proposal, implementation, and validation," in Int. Symp. Electromagn. Compatibil., Aug. 8-12, 2005, vol. 2, pp. 672-677.
3. S. Huq, V. Arumugham, Z. Yang, and B. Ross, "Power integrity analysis using IBIS," in Buffer Issue Resolution Documents (BIRD) 95 [Online]. Available: http://www.vhdl.org/pub/ibis/birds/bird95.6.txt
4. A. Muranyi, "Gate modulation effect," IBIS Buffer Issue Resolution Documents (BIRD) 97. [Online]. Available: http://www.vhdl.Org/pub/ibis/birds/bird97.2.txt
5. I. Stievano, I. Maio, and F. Canavero, "Parametric macromodels of digital I/O ports," IEEE Trans. Adv. Packag., vol. 25, no. 2, pp. 255-264, May 2002.
6. I. Stievano, I. Maio, and F. Canavero, "Mpilog, macromodeling via parametric identification of logic gates," IEEE Trans. Adv. Packag. vol. 27, no. 1, pp. 15-23, Feb. 2004.
7. B. Mutnury, M. Swantinathan, and J. Libous, "Macromodeling of nonlinear digital I/O drivers," IEEE Trans. Adv. Packag., vol. 29, no. 1, pp. 102-113, Feb. 2006.
8. R. Senthinathan and J. Prince, Simultaneous Switching Noise of CMOS Devices and Systems. Boston, MA: Kluwer Academic, 1994.
9. B. Young, Digital Signal Integrity: Modeling and Simulation With Interconnects and Packages. Upper Saddle River, NJ: Prentice Hall, 2000.
10. M. Perrott, HSPICE Toolbox for MATLAB, MIT High Speed Circuits and System (HSCS) Group 2004 [Online]. Available: http://www-mtl.mit.edu/ researchgroups/perrottgroup/tools.html
11. "DDR2 SDRAM Part Catalog.," MICRON Inc. [Online]. Available: http://www.micron.com/products/dram/ddr2/partlist.aspx