Mπlog, macromodeling via parametric identification of logic gates

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 1, 2004, Pages 15-23

  Stievano, Igor S ^a   Maio, Ivan A ^a   Canavero, Flavio G ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Circuit modeling; Digital integrated circuits; Electromagnetic compatibility; I O ports; Macromodeling; Signal integrity; System identification

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTROMAGNETIC COMPATIBILITY; LOGIC GATES; MATHEMATICAL MODELS; POWER ELECTRONICS;

MACROMODELLING; NONLINEAR PARAMETRIC MODEL; PARAMETRIC IDENTIFICATION; SIGNAL INTEGRITY;

ELECTRONICS PACKAGING;

EID: 2442602408     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.825475     Document Type: Article

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