VHDL vs. Bluespec system verilog: A case study on a Java embedded architecture

Proceedings of the ACM Symposium on Applied Computing

Volumn , Issue , 2008, Pages 1492-1497

  Gruian, Flavius ^a   Westmijze, Mark ^b  

^a LUND UNIVERSITY   (Sweden)

^b UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Bluespec; Embedded systems; Java processor

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER PROGRAMMING LANGUAGES; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUITS; JAVA PROGRAMMING LANGUAGE; LINGUISTICS; PIPELINE PROCESSING SYSTEMS; QUERY LANGUAGES;

ABSTRACTION LEVELS; ASSEMBLY LANGUAGES; BLUESPEC; BYTE CODES; CASE STUDIES; DESIGN EXPERIENCES; DESIGN FLOWS; EMBEDDED ARCHITECTURES; GARBAGE COLLECTORS; HARDWARE DESIGNS; JAVA PROCESSOR; MEMORY ALLOCATIONS; MEMORY MANAGEMENT UNITS; QUALITATIVE MEASURES; VERILOG;

EMBEDDED SYSTEMS;

EID: 56749101675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1363686.1364037     Document Type: Conference Paper

References (18)

1. IEEE Standard VHDL Language Reference Manual: IEEE Std 1076-1998. IEEE, August 1994.
2. Bluespec, Inc. http://www.bluespec.com, 2007.
3. N. Dave. Designing a processor in Bluespec. Master's thesis, MIT, Cambridge, MA, January 2005.
4. N. Dave, M. Pellauer, S. Gerding, and Arvind. 802.11a transmitter: A case study in microarchitectural exploration. In International Conference on Formal Methods and Models for Codesign (MEMOCODE'06), pages 59-68, July 2006.
5. A. Gerstlauer, R. Domer, J. Peng, and D. D. Gajski. System Design - A Practical Guide with SpecC. Kluwer academic, 2001.
6. F. Gruian, P. Andersson, K. Kuchcinski, and M. Schoeberl. Automatic generation of application-specific systems based on a micro-programmed java core. In 20th Symposium on Applied Computing, Embedded Systems Track, 2005.
7. F. Gruian and Z. Salcic. Designing a concurrent hardware garbage collector for small embedded systems. In Asia-Pacific Computer Systems Architecture Conference, pages 281-294, 2005.
8. F. Gruian and M. Westmijze. BluEJAMM: A Bluespec embedded Java architecture with memory management. In SYNASC'07 Real-Time and Embedded Systems workshop, September 2007.
9. F. Gruian and M. Westmijze. BlueJEP: A flexible and high-performance Java embedded processor. In The 5th Int'l Workshop on Java Technologies for Real-time and Embedded Systems, JTRES'07, pages 222-229, September 26-29 2007.
10. J. C. Hoe and Arvind. Hardware synthesis from term rewriting systems. In VLSI '99: Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration, pages 595-619, Deventer, The Netherlands, The Netherlands, 2000.
11. M. Schoeberl. JOP: A java optimized processor. In Workshop on Java Technologies for Real- Time and Embedded Systems, November 2003.
12. M. Schoeberl. A time predictable instruction cache for a Java processor. In On the Move to Meaningful Internet Systems 2004: Workshop on Java Technologies for Real- Time and Embedded Systems (JTRES 2004), volume 3292 of LNCS, pages 371-382, Agia Napa, Cyprus, October 2004. Springer.
13. M. Schoeberl. JOP: A Java Optimized Processor for Embedded Real-Time Systems. PhD thesis, Vienna University of Technology, January 2005.
14. SystemC. the open systemC initiative. http://www.systemc.org.
15. D. E. Thomas and P. R. Moorby. The Verilog Hardware Description Language. Springer, 5 edition, June 2002.
16. R. E. Wunderlich and J. C. Hoe. In-system FPGA prototyping of an Itanium microarchitecture. In International Conference on Computer Design, October 2004.
17. Xilinx. ChipScope Pro Software and Cores User Guide, v9.1.01 edition, January 2007.
18. Xilinx Inc. http://www.xilinx.com/, 2007.