CMOS / CMOL architectures for spiking cortical column

Proceedings of the International Joint Conference on Neural Networks

Volumn , Issue , 2008, Pages 2441-2448

  Gao, Changjian ^a   Zaveri, Mazad S ^a   Hammerstrom, Dan ^a  

^a Portland State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE PROCESSING; COLUMNS (STRUCTURAL); COST EFFECTIVENESS; LEARNING ALGORITHMS; LEARNING SYSTEMS;

ASSOCIATIVE MEMORIES; CMOL ARCHITECTURES; COLUMN MODELS; DIGITAL CMOS; MIXED SIGNALS; MOLECULAR CIRCUITRIES;

NEURAL NETWORKS;

EID: 56349150964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2008.4634138     Document Type: Conference Paper

References (28)

1. V. Mountcastle, Perceptual Neuroscience - The Cerebral Cortex. Cambridge, MA: Harvard University Press, 1998.
2. V. Braitenberg and A. Schüz, Cortex: Statistics and Geometry of Neuronal Connectivity. Springer-Verlag, 1998.
3. U. Rückert, "An associative memory with neural architecture and its VLSI, implementation," presented at HICSS-24, Koloa, Hawaii, 1990.
4. A. Heittmann and U. Rückert, "Mixed mode VLSI implementation of a neural associative memory," presented at MicroNeuro '99, 1999.
5. J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, "Ge/Si nanowire heterostructures as high-performance field-effect transistors," Nature, vol. 441, pp. 489-493, 2006.
6. P. J. Kuekes, D. R. Stewart, and R. S. Williams, "The crossbar latch: logic value storage, restoration, and inversion in crossbar circuits," Journal of Applied Physics, vol. 97, pp. 034301-1-5, 2005.
7. D. J. Resnick, W. J. Dauksher, D. Mancini, K. J. Nordquist, T. C. Bailey, S. Johnson, N. Stacey, J. G. Ekerdt, C. G. Willeon, and S. V. Sreenivasan, "Imprint lithography for integrated circuit fabrication," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol. 21, pp. 2624, 2003.
8. K. K. Likharev and D. V. Strukov, "CMOL: devices, circuits, and architectures," in Introduction to Molecular Electronics, G. Cuniberti and et al., Eds. Berlin: Springer, 2005, pp. 447-478.
9. G. Palm, F. Schwenker, F. T. Sommer, and A. Strey, "Neural associative memories," in Associative Processing and Processors. Los Alamitos, CA.: IEEE Computer Society, 1997, pp. 284-306.
10. D. Willshaw, "Tolerance of a self-organizing neural network," Neural Computation, pp. 911-936, 1997.
11. C. Gao and D. Hammerstrom, "CMOL based cortical models," in process for Emerging Brain-Inspired Nano-Architectures, V. Beiu and U. Rückert, Eds., 2006.
12. D. George and J. Hawkins, "A hierarchical Bayesian model of invariant pattern recognition in the visual cortex," presented at IJCNN '05, 2005.
13. W. Gerstner, "Spiking Neurons," in Pulsed Neural Networks, W. Maass and C. M. Bishop, Eds. Cambridge, MA: MIT Press, 1998, pp. 3-53.
14. ITRS, "International Technology Roadmap for Semiconductors 2005 edition - Executive Summary," 2005.
15. R. Figueiredo, P. A. Dinda, and J. Fortes, "Guest Editors' Introduction: Resource Virtualisation Renaissance," Computer, vol. 38, pp. 28-31, 2005.
16. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity," IEEE Transactions on Neural Networks, vol. 17, pp. 211-221, 2006.
17. U. Rückert, "ULSI architectures for artificial. neural networks," Micro, IEEE, vol. 22, pp. 10-19, 2002.
18. T. Schoenauer, S. Atasoy, M. Nassa, and H. Klar, "NeuroPipe-chip: a digital neuro-processor for spiking neural networks," IEEE Trans. on Neural Networks, vol. 13, pp. 205-213, 2002.
19. A. Bofill-i-Petit and A. F. Murray, "Synchrony detection by analogue VLSI neurons with bimodal STDP synapses," presented at NIPS 2003, 2003.
20. K. A. Boahen, "Point-to-point connectivity between neuromorphic chips using address events," IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, vol. 47, pp. 416-434, 2000.
21. C. Gao and D. Hammerstrom, "Cortical models onto CMOL and CMOS - architectures and performance/price," IEEE Tran. on Circuits and Systems - I: Regular Papers - Special Issue on Nanoelectronic Circuits and Nanoarchitectures, vol. 54, pp. 2502-2515, 2007.
22. S. S. Iyer, J. E. Barth. Jr, P. C. Parries, J. P. Norum, J. P. Rice, L. R. Logan, and D. Hoyniak, "Embedded DRAM: technology platform for the Blue Gene/L chip," IBM J. Res. & Dev., vol. 49, pp. 333-350, 2005.
23. Ö. Türel, J. H. Lee, X. Ma, and K. K. Likharev, "Architectures for nanoelectronic implementation of artificial neural networks: new results," Neurocomputing, vol., 64, pp. 271-283, 2005.
24. N. Weste and D. Harris, CMOS VLSI Design - A Circuits and Systems Perspective, 3rd ed: Addison Wesley, 2004.
25. J. J. Hopfield and C. D. Brody, "What is a moment? Transient synchrony as a collective mechanism for spatiotemporal integration," Proc. Natl. Acad. Sci., vol. 98, pp. 1282-1287, 2001.
26. E. M. Izhikevich, "Polycronization: Computation with spikes," Neural Computation, vol. 18, pp. 245-282, 2006.
27. S. M. Bohte, H. A. La. Poutre, and J. N. Kok, "Unsupervised clustering with spiking neurons by sparse temporal coding and multilayer RBF networks," IEEE Trans. on Neural Networks, vol. 13, pp. 426-435, 2002.
28. M. J. Hudak, "RCE classifiers: theory and practice," Cybernetics and Systems, vol. 23, pp. 483-515, 1993.