Automatic identification of defect patterns in semiconductor wafer maps using spatial correlogram and dynamic time warping

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 4, 2008, Pages 625-637

  Jeong, Young Seon ^a   Kim, Seong Jun ^b   Jeong, Myong K ^a  

^a DEPARTMENT OF INDUSTRIAL AND SYSTEMS ENGINEERING   (United States)

^b Gangneung Wonju National University   (South Korea)

Author keywords

Dynamic time warping; Join count (JC) statistics; Spatial autocorrelation; Spatial correlogram; Wafer map

Indexed keywords

AUTOCORRELATION; AUTOMATIC INDEXING; AUTOMATION; CORRELATION DETECTORS; DEFECTS; ELECTRONIC DATA INTERCHANGE; ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS; INTEGRATED CIRCUITS; LOCATION; OBJECT RECOGNITION; WAVELET TRANSFORMS; WEAVING;

AUTOMATIC CLASSIFICATIONS; AUTOMATIC IDENTIFICATIONS; CLASSIFICATION OF DEFECTS; CORRELOGRAM; DEFECT LOCATIONS; DEFECTIVE CHIPS; DYNAMIC TIME WARPING; DYNAMIC TIME WARPING ALGORITHMS; GRAPHICAL ILLUSTRATIONS; INTEGRATED CIRCUIT FABRICATIONS; OPTIMAL WEIGHTS; RANDOM NOISES; RANDOMNESS TESTS; ROBUST PERFORMANCES; SEMICONDUCTOR WAFERS; SIMULATED DATA SETS; SPATIAL AUTOCORRELATION; SPATIAL AUTOCORRELATIONS; SPATIAL CORRELOGRAM; SPATIAL DEPENDENCES; SPATIAL PATTERNS; WAFER MAP; WAFER MAPS;

MAPS;

EID: 55649109843     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2008.2005375     Document Type: Article

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