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Volumn , Issue , 2008, Pages 737-740

CMOL-based cellular neural networks and parallel processor for future image processing

Author keywords

Cellular neural network; CMOL; Image processing; Molecular electronics

Indexed keywords

DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL IMAGE STORAGE; DYNAMICS; IMAGE CLASSIFICATION; IMAGE PROCESSING; IMAGING SYSTEMS; MOLECULAR ELECTRONICS; NANOTECHNOLOGY; NEURAL NETWORKS; VEGETATION;

EID: 55349099493     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2008.221     Document Type: Conference Paper
Times cited : (2)

References (10)
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    • Likharev, K.K.1    Strukov, D.B.2
  • 2
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    • (2005) Nanotechnol , vol.16 , pp. 137-148
    • Strukov, D.B.1    Likharev, K.K.2
  • 3
    • 25144480834 scopus 로고    scopus 로고
    • CMOL cross Nets as pattern classifiers
    • J. H. Lee and K. K. Likharev, "CMOL cross Nets as pattern classifiers", IWANN 2005, vol. 3512, pp. 446-454.
    • IWANN 2005 , vol.3512 , pp. 446-454
    • Lee, J.H.1    Likharev, K.K.2
  • 4
    • 18744373862 scopus 로고    scopus 로고
    • CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
    • D. B. Strukov and K. K. Likharev, "CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices", Nanotechnol., vol. 16, pp. 888-900, 2005.
    • (2005) Nanotechnol , vol.16 , pp. 888-900
    • Strukov, D.B.1    Likharev, K.K.2
  • 5
    • 36348967261 scopus 로고    scopus 로고
    • Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing
    • D. B. Strukov and K. K. Likharev, "Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing," IEEE Trans. Nanotechnol., vol. 6, no. 6, pp. 696-710, 2007.
    • (2007) IEEE Trans. Nanotechnol , vol.6 , Issue.6 , pp. 696-710
    • Strukov, D.B.1    Likharev, K.K.2
  • 6
    • 0024092072 scopus 로고
    • Cellular neural networks: Theory
    • L.O. Chua, L. Yang, "Cellular neural networks: Theory," IEEE Trans. Circuit & System, vol. 35, no. 1, pp. 1273-1290, 1988.
    • (1988) IEEE Trans. Circuit & System , vol.35 , Issue.1 , pp. 1273-1290
    • Chua, L.O.1    Yang, L.2
  • 8
    • 34548833277 scopus 로고    scopus 로고
    • A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing
    • B. Khailanyl, T. Williams, J. Lin et al., "A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing," ISSCC 2008, no. 15-2, pp. 272-274.
    • (2008) ISSCC , Issue.15 -2 , pp. 272-274
    • Khailanyl, B.1    Williams, T.2    Lin, J.3
  • 9
    • 33845585014 scopus 로고    scopus 로고
    • A 40GOPS 250mW massively parallel processor based on matrix architecture
    • M. Nakajima et al., "A 40GOPS 250mW massively parallel processor based on matrix architecture," ISSCC Dig. Tech. Papers, pp. 410, 2006.
    • (2006) ISSCC Dig. Tech. Papers , pp. 410
    • Nakajima, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.