A 40GOPS 250mW massively parallel processor based on matrix architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Nakajima, Masami ^a   Noda, Hideyuki ^a   Dosaka, Katsumi ^a   Nakata, Kiyoshi ^a   Higashida, Motoki ^a   Yamamoto, Osamu ^a   Mizumoto, Katsuya ^a   Kondo, Hiroyuki ^a   Shimazu, Yukihiko ^a   Arimoto, Kazutami ^a   Saitoh, Kazunori ^a   Shimizu, Toru ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; NETWORK ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE;

CLOCK FREQUENCY; MATRIX ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 33845585014     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. B.Flachs et al., "A Streaming Processor Unit for a CELL Processor," ISSCC Dig. Tech. Papers, pp. 134-135, Feb. 2005.
2. A.A.Bright et al., "Creating the BlueGene/L Supercomputer from Low-Power SoC ASICs.," ISSCC Dig. Tech. Papers, pp. 188-189, Feb., 2005.
3. http://www.es.jamstec.go.jp/esc/eng/Hardware/arithmetic.html