SCOPUS 정보 검색 플랫폼

2008 8th IEEE Conference on Nanotechnology, IEEE-NANO

Volumn , Issue , 2008, Pages 609-612

CMOS Integrated single electron transistor electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out

(4) Gurrieri, Thomas M a Carroll, Malcolm S a Lilly, Michael P a Levy, James E a

a SANDIA NATIONAL LABORATORIES (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; CMOS SOI TECHNOLOGIES; CURRENT MODES; NANO-SECONDS; OPERATION SPEEDS; POWER DISSIPATIONS; RADIO FREQUENCIES; ROOM TEMPERATURES; SINGLE ELECTRON TRANSISTORS; SPICE MODELS; SUB MICRONS; VOLTAGE MODES;

CAPACITANCE MEASUREMENT; DIGITAL CIRCUITS; ELECTRON TRAPS; INTEGRATED CIRCUIT MANUFACTURE; NANOTECHNOLOGY; NETWORKS (CIRCUITS); SILICON;

TRANSIENTS;

EID: 55349092667 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/NANO.2008.183 Document Type: Conference Paper

Times cited : (14)

References (6)

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2
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- April
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3
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- Akira Fujiwara, a_ Hiroshi Inokawa, Kenji Yamazaki, Hideo Namatsu, and Yasuo Takahashib, "Single electron tunneling transistor with tunable barriers using silicon nanowire metal-oxide-semiconductor field-effect transistor", Applied Physics Letters, vol. 88, 053121, January 30, 2006

4
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- Silicon single-electron quantum-dot transistor switch operating at room temperature
- March 9
- Lei Zhuang, Lingjie Guo, and Stephen Y. Chou, "Silicon single-electron quantum-dot transistor switch operating at room temperature", Applied Physics Letters, vol. 72, pp. 1205-1207, March 9, 2007
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- Lei, Z.¹ Guo, L.² Chou, S.Y.³

5
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- Low power CMOS dynamic latch comparators
- October 15-17
- P. Uthaichana and E. Leelarasmee, "Low power CMOS dynamic latch comparators", TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region, vol. 2, pp. 605-608, October 15-17 2003
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- Uthaichana, P.¹ Leelarasmee, E.²

6
- 0031553256
- Robust high-accuracy high-speed continuous-time CMOS current comparator
- December
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