-
1
-
-
54949121682
-
-
http://www.xilinx.com
-
-
-
-
2
-
-
84863411830
-
A System Level Resource Estimation Tool for FPGAs
-
Shi, C., Hwang, J., McMillan, S., Root, A., and Singh, V., "A System Level Resource Estimation Tool for FPGAs", International Conference on Field Programmable Logic and Applications (FPL), 2004.
-
(2004)
International Conference on Field Programmable Logic and Applications (FPL)
-
-
Shi, C.1
Hwang, J.2
McMillan, S.3
Root, A.4
Singh, V.5
-
3
-
-
4444254091
-
An Area Estimation Methodology for FPGA Based Designs at SystemC-Level
-
June
-
Brandolese, C., Fornaciari, W., and Salice, F., "An Area Estimation Methodology for FPGA Based Designs at SystemC-Level", Design Automation Conference (DAC), June 2004.
-
(2004)
Design Automation Conference (DAC)
-
-
Brandolese, C.1
Fornaciari, W.2
Salice, F.3
-
4
-
-
0038081313
-
Fast Prototyping of Reconfigurable Architectures From a C Program
-
Bilavarn, S., Gogniat, G., Philippe, J., and Bossuet, L., "Fast Prototyping of Reconfigurable Architectures From a C Program", International Symposium on Circuits and Systems (ISCAS), 2003.
-
(2003)
International Symposium on Circuits and Systems (ISCAS)
-
-
Bilavarn, S.1
Gogniat, G.2
Philippe, J.3
Bossuet, L.4
-
5
-
-
33745189089
-
Compile-Time Area Estimation for LUT-Based FPGAs
-
January
-
Kulkarni, D., Najjar, W., Rinker, R., and Kurdahi, F., "Compile-Time Area Estimation for LUT-Based FPGAs", ACM Transactions on Design Automation of Electronic Systems, January 2006.
-
(2006)
ACM Transactions on Design Automation of Electronic Systems
-
-
Kulkarni, D.1
Najjar, W.2
Rinker, R.3
Kurdahi, F.4
-
6
-
-
84893790504
-
Accurate Area and Delay Estimators for FPGAs
-
Nayak, A., Haldar, M., Choudhary, A., and Banerjee, P., "Accurate Area and Delay Estimators for FPGAs", Design, Automation, & Test in Europe (DATE), 2002.
-
(2002)
Design, Automation, & Test in Europe (DATE)
-
-
Nayak, A.1
Haldar, M.2
Choudhary, A.3
Banerjee, P.4
-
7
-
-
0036050384
-
FPGA Resource and Timing Estimation from Matlab Execution Traces
-
May
-
Bjureus, P., Millberg, M., and Jantsch, A., "FPGA Resource and Timing Estimation from Matlab Execution Traces", CODES, May 2002.
-
(2002)
CODES
-
-
Bjureus, P.1
Millberg, M.2
Jantsch, A.3
-
8
-
-
33745834804
-
Fast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores
-
February
-
Milder, P., Ahmed, M., Hoe, J., and Puschel, M., "Fast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores", FPGA Conference, February 2006.
-
(2006)
FPGA Conference
-
-
Milder, P.1
Ahmed, M.2
Hoe, J.3
Puschel, M.4
-
9
-
-
0030651645
-
ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications
-
Xu, M. and Kurdahi, F., "ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications", ASP-DAC, 1997.
-
(1997)
ASP-DAC
-
-
Xu, M.1
Kurdahi, F.2
-
10
-
-
54949095032
-
-
http://www.verific.com
-
-
-
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