Compile-time area estimation for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems

Volumn 11, Issue 1, 2006, Pages 104-122

  Kulkarni, Dhananjay ^a,d   Najjar, Walid A ^a,d   Rinker, Robert ^b   Kurdahi, Fadi J ^c,e  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF IDAHO   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d University of California Riverside   (United States)

^e University of California at Irvine   (United States)

Author keywords

Compiler optimization; Reconfigurable computing; Resource estimation

Indexed keywords

EID: 33745189089     PISSN: 10844309     EISSN: 10844309     Source Type: Journal    
DOI: 10.1145/1124713.1124721     Document Type: Article

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