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Volumn 2001-January, Issue , 2001, Pages 80-86

A new reseeding technique for LFSR-based test pattern generation

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; HARDWARE;

EID: 5444246652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2001.937823     Document Type: Conference Paper
Times cited : (13)

References (13)
  • 5
    • 0032314715 scopus 로고    scopus 로고
    • BIST for systems-on-a-chip
    • Elsevier, December
    • H. J. Wunderlich, "BIST for systems-on-a-chip", Integration, The VLSI Journal, vol. 26, (no. 1-2), Elsevier, December 1998, pp. 55-78.
    • (1998) Integration, the VLSI Journal , vol.26 , Issue.1-2 , pp. 55-78
    • Wunderlich, H.J.1
  • 6
    • 0002446741 scopus 로고
    • LFSR-coded test patterns for scan design
    • Munich, Germany, April
    • B. Koenemann, "LFSR-Coded Test Patterns for Scan Design", Proc. of European Test Conference, Munich, Germany, April 1991, pp 237-242.
    • (1991) Proc. of European Test Conference , pp. 237-242
    • Koenemann, B.1
  • 7
    • 84961240995 scopus 로고
    • Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers
    • Baltimore, MD, USA, Sept
    • S. Hellebrand, S. Tarnick, B. Courtois and J. Rajski, "Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", Proc. of International Test Conference, Baltimore, MD, USA, Sept. 1992, pp. 120-129.
    • (1992) Proc. of International Test Conference , pp. 120-129
    • Hellebrand, S.1    Tarnick, S.2    Courtois, B.3    Rajski, J.4
  • 9
    • 0029252184 scopus 로고
    • Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
    • February
    • S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE Transactions on Computers, Vol. 44, No. 2, February 1995, pp. 223-233.
    • (1995) IEEE Transactions on Computers , vol.44 , Issue.2 , pp. 223-233
    • Hellebrand, S.1    Rajski, J.2    Tarnick, S.3    Venkataraman, S.4    Courtois, B.5
  • 10
    • 0026820276 scopus 로고
    • A multiple seed linear feedback shift register
    • February
    • J. Savir and W. H. McAnney, "A Multiple Seed Linear Feedback Shift Register", IEEE Trans. on Computers, vol. 41, no. 2, February 1992, pp. 250-252.
    • (1992) IEEE Trans. on Computers , vol.41 , Issue.2 , pp. 250-252
    • Savir, J.1    McAnney, W.H.2
  • 11
    • 0029213993 scopus 로고
    • An apparatus for pseudo-deterministic testing
    • Princeton, NJ, USA, April-May
    • S. K. Mukund, E. J. McCluskey and T. R. N. Rao, "An Apparatus for Pseudo-Deterministic Testing", Proc. of 13th VLSI Test Symposium, Princeton, NJ, USA, April-May 1995, pp. 125-131.
    • (1995) Proc. of 13th VLSI Test Symposium , pp. 125-131
    • Mukund, S.K.1    McCluskey, E.J.2    Rao, T.R.N.3
  • 13
    • 0030651782 scopus 로고    scopus 로고
    • Methods to reduce test application time for accumulator-based self-test
    • Monterey, CA, USA, April-May
    • A. P. Stroele and F. Mayer, "Methods to Reduce Test Application Time for Accumulator-based Self-Test", Proc. of VLSI Test Symposium, Monterey, CA, USA, April-May 1997, pp. 48-53.
    • (1997) Proc. of VLSI Test Symposium , pp. 48-53
    • Stroele, A.P.1    Mayer, F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.