Identifying energy-efficient concurrency levels using machine learning

Proceedings - IEEE International Conference on Cluster Computing, ICCC

Volumn , Issue , 2007, Pages 488-495

  Curtis Maury, Matthew ^a,c   Singh, Karan ^b,c   McKee, Sally A ^b   Blagojevic, Filip ^a   Nikolopoulos, Dimitrios S ^a   De Supinski, Bronis R ^c   Schulz, Martin ^c  

^a Virginia Polytechnic Institute and State University   (United States)

^b Cornell University ^*  (United States)

^c LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; ARTIFICIAL INTELLIGENCE; ARTS COMPUTING; COMPUTER SOFTWARE; ELECTRIC FAULT LOCATION; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; LEARNING SYSTEMS; MULTITASKING; NETWORK PROTOCOLS; NEURAL NETWORKS; ROBOT LEARNING; SENSOR NETWORKS; SOFTWARE RELIABILITY;

ARTIFICIAL NEURAL NETWORKS; CLUSTER COMPUTING; CONCURRENCY LEVELS; DEGREE OF PARALLELISM; END USERS; ENERGY-EFFICIENT; HARDWARE STRUCTURES; INTERNATIONAL CONFERENCES; LOW POWERS; MACHINE-LEARNING; MULTI CORES; MULTI-THREADED; OPERATING SYSTEMS; PARALLEL PROGRAMS; POWER CONSUMPTION; SCIENTIFIC APPLICATIONS; SINGLE-THREADED; SOFTWARE COMPONENTS; SOFTWARE DEVELOPERS; THREAD-LEVEL PARALLELISM; TO MANY; TRAINING PHASE;

CONCURRENCY CONTROL;

EID: 53349118980     PISSN: 15525244     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CLUSTR.2007.4629274     Document Type: Conference Paper

References (17)

1. B. Saha, A.-R. Adl-Tabatabai, A. Ghuloum, M. Rajagopalan, R. L. Hudson, L. Petersen, V. Menon, B. Murphy, T. Shpeisman, E. Sprangle, A. Rohillah, D. Carmean, and J. Fang, "Enabling Scalability and Performance in a Large Scale CMP Environment," in Proc. of the European Conference on Computer Systems, Lisbon, Portugal, Mar. 2007.
2. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. J. S. Venkataraman, Y. Hoskote, and N. Borkar, "An 80-tile 1.28TFL0PS Network-on-Chip in 65nm. CMOS," in Proc. of the International Solid State Circuits Conference, San Francisco, CA, 2007, pp. 5-7.
3. M. Curtis-Maury, J. Dzierwa, C. D. Antonopoulos, and D. S. Nikolopoulos, "Online Power-Performance Adaptation of Multithreaded Programs using Hardware Event-Based Prediction," in Proc. of the 20th ACM International Conference on Supercomputing, Queensland, Australia, June 2006.
4. B. Lee and D. Brooks, "Accurate and Efficient Regression Modelling for Microarchitectural Performance and Power Prediction," in Proc. of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, June 2006.
5. J. Li and J. Martínez, "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors," in Proc. of the 12th International Symposium on High-Performance Computer Architecture, Austin, TX, Feb. 2006.
6. E. Ipek, S. A. McKee, B. R. de Supinski, M. Schulz, and R. Caruana, "Efficiently Exploring Architectural Design Spaces via Predictive Modeling," in Proc. of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, June 2006.
7. B. Lee, D. Brooks, B. R. de Supinski, M. Schulz, K. Singh, and S. A. McKee, "Methods of Inference and Learning for Performance Modeling of Parallel Applications," in Proc. of the International Symposium on Principles and Practices of Parallel Programming, Mar. 2007.
8. G. Marin and J. Mellor-Crummey, "Cross-architecture performance predictions for scientific applications using parameterized models," in Proc.ACM International Conference on Measurement and Modeling of Computer Systems, June 2004, pp. 2-13.
9. L. Carrington, N. Wolter, A. Snavely, and C. Lee, "Applying an automatic framework to produce accurate blind performance predictions of full-scale HPC applications," in Department of Defense Users Group Conference, June 2004.
10. T. Yang, X. Ma, and F. Mueller, "Cross-platform performance prediction of parallel applications using partial execution," in Proc. IEEE/ACM Supercomputing International Conference on High Performance Computing, Networking, Storage and Analysis, Nov. 2005.
11. H. Jin, M. Frumkin, and J. Yan, "The OpenMP Implementation of NAS Parallel Benchmarks and its Performance," NASA Ames Research Center," Technical Report NAS-99-011, Oct. 1999.
12. R. M. Yoo, H. Lee, K. Chow, and H.-H. S. Lee, "Constructing a nonlinear model with neural networks for workload characterization." in IISWC, 2006, pp. 150-159.
13. C. Dubach, J. Cavazos, B. Franke, G. Fursin, M. F. O'Boyle, and O. Temam, "Fast compiler optimisation evaluation using code-feature based performance prediction," in CF '07: Proceedings of the 4th international conference on Computing frontiers. New York, NY, USA: ACM Press, 2007, pp. 131-142.
14. T. Mitchell, Machine Learning. Boston, MA: WCB/McGraw Hill, 1997.
15. R. Caruana, S. Lawrence, and C. Giles, "Overfitting in neural nets: Backpropagation, conjugate gradient, and early stopping," in Proc. Neural Information Processing Systems Conference, Oct. 2000.
16. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically Characterizing Large Scale Program. Behavior," in Proc. of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2002.
17. M. Curtis-Maury, J. Dzierwa, C. D. Antonopoulos, and D. S. Nikolopoulos, "Online Strategies for High-Performance Power-Aware Thread Execution, on Emerging Multiprocessors," in Proc. of the Workshop on High-Performance Power-Aware Computing, Rhodes, Greece, Apr. 2006.