On the performance limits of emerging nano-MOS transistors: A simulation study

2007 7th IEEE International Conference on Nanotechnology - IEEE-NANO 2007, Proceedings

Volumn , Issue , 2007, Pages 530-535

  Tsuchiya, Hideaki ^a,b   Fujii, Kazuya ^b   Mori, Takashi ^b   Azuma, Yusuke ^b   Okuda, Kyosuke ^b   Miyoshi, Tanroku ^a,b  

^a IEEE

^b KOBE UNIVERSITY   (Japan)

Author keywords

Ballistic transport; Multi gate architecture; NanoMOS transistors; New channel materials; Quantum corrected Monte Carlo method; Technology boosters

Indexed keywords

BALLISTICS; CMOS INTEGRATED CIRCUITS; EXPLOSIVES; GERMANIUM; METALS; MONTE CARLO METHODS; NANOTECHNOLOGY; SILICON; TECHNOLOGY; THREE DIMENSIONAL; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSPORT PROPERTIES;

BALLISTIC TRANSPORT; BALLISTIC TRANSPORTS; DEVICE ARCHITECTURES; DEVICE PERFORMANCES; DRIVE CURRENTS; HIGH MOBILITY CHANNELS; INTERNATIONAL CONFERENCES; LATERAL QUANTUM CONFINEMENT; MONTE CARLO SIMULATION; MOS TRANSISTORS; MOSFETS; MULTI-GATE ARCHITECTURE; N-CHANNEL MOSFETS; NANO SCALING; NANOMOS TRANSISTORS; NEW CHANNEL MATERIALS; PARTICLE METHODS; PERFORMANCE LIMITS; QUANTUM-CORRECTED MONTE CARLO METHOD; QUASI-BALLISTIC TRANSPORT; SI DEVICES; SIMULATION STUDIES; SOURCE AND DRAIN; TECHNOLOGY BOOSTERS; THREE DIMENSIONAL (3D); ULTRA-THIN BODIES;

MOSFET DEVICES;

EID: 52949128022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2007.4601247     Document Type: Conference Paper

References (11)

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