Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Microelectronic Engineering

Volumn 85, Issue 10, 2008, Pages 2146-2149

  Gregoire, M ^a   Juhel, M ^a   Vannier, P ^a   Normandon, P ^a  

^a STMICROELECTRONICS   (France)

Author keywords

Annealing; Cu interconnects; Impurities; Microstructure; Stress voiding

Indexed keywords

COPPER ALLOYS; COPPER PLATING; EPITAXIAL GROWTH; OPTICAL INTERCONNECTS;

300 MM WAFERS; ANNEALING; CRITICAL PATHS; CU DEPOSITION; CU INTERCONNECTS; DUAL-DAMASCENE INTERCONNECTS; ELECTRICAL RESULTS; HOT PLATES; IMPURITIES; INTERFACE PROPERTIES; MICRO-STRUCTURAL CHARACTERIZATION; MICROSTRUCTURE; MULTI-LEVEL; STRESS-INDUCED VOIDING; STRESS-VOIDING; VOID NUCLEATION;

COPPER;

EID: 52149086354     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.04.029     Document Type: Article

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