Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systms - Digest of Papers, SiRF

Volumn , Issue , 2008, Pages 151-154

  Kerr, Daniel C ^a   Gering, Joseph M ^a   McKay, Thomas G ^b   Carroll, Michael S ^a   Neve, César Roda ^c   Raskin, Jean Pierre ^c  

^a RF MICRO DEVICES   (United States)

^b RFMD   (United States)

^c UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

Harmonic distortion; High resistivity Si substrate; Non linear measurements; RF switches; SOI technology

Indexed keywords

900 MHZ; COPLANAR WAVEGUIDE STRUCTURES; HIGH-RESISTIVITY SI SUBSTRATE; INPUT POWERS; NON-LINEAR MEASUREMENTS; RF SWITCHES; RF SYSTEMS; SI SUBSTRATES; SILICON SUBSTRATES; SOI TECHNOLOGY;

ELECTRONICS INDUSTRY; EPITAXIAL GROWTH; HARMONIC DISTORTION; INTEGRATED CIRCUITS; LITHOGRAPHY; NONMETALS; RADIOFREQUENCY SPECTROSCOPY; SILICON; SUBSTRATES; WAVEGUIDES;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 52049096665     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2008.44     Document Type: Conference Paper

References (12)

1. C. Tinella, O. Richard, A. Cathelin, F. Reaute, S. Majcherczak, F. Blanchet, and D. Belot, "0.13 μm CMOS SOI SP6T antenna switch for multi-standard handsets," Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Jan. 18-20, p. 58, 2006,
2. T. G. McKay, M. S. Carroll, J. Costa, C. Iversen, D. C. Kerr, and Y. Remoundos, "Linear cellular antenna switch for highly integrated SOI front-end," IEEE Intl. SOI Conf., 2007.
3. "Single-pole four-throw high-power switch," RF1450 Data sheet, http://www.rfmd.com/pdfs/1450DS.pdf.
4. A. C. Reyes, S. M. El-Ghazaly, S. J. Dorn, M. Dydyk, D. K. Schroder, and H. Patterson, "Coplanar waveguides and microwave inductors on silicon substrate," Trans. Microwave Theory Tech., 43(9), pp. 2016-2021, 1995.
5. 2 interface layer effects on microwave loss of high-resistivity CPW line," Microwave and Guided Wave Letters, pp. 10-12, 1999.
6. H. S. Gamble, B. M. Armstrong, S. J. N. Mitchell, Y. Wu, V. F. Fusco, and J. A. C. Stewart, "Low-loss CPW lines on surface stabilized high-resistivity silicon," Microwave Guided Wave Lett., 9(10), pp. 395-397, 1999.
7. th Microwave Measurement Symposium, November 2007.
8. S. Hirae, M. Hirose, Y. Osaka, "Energy distribution of trapping states in polycrystalline silicon," J. Appl. Phys., 51(2), pp. 1043-1047, 1980.
9. D. Lederer, R. Lobet and J.-P. Raskin, "Enhanced high resistivity SOI wafers for RF applications," IEEE Intl. SOI Conf., pp. 46-47, 2004.
10. D. Lederer and J.-P. Raskin, "New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity," IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005.
11. D. Lederer, B. Aspar, C. Laghaé and J.-P. Raskin, "Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate," IEEE International SOI Conference, pp. 29-30, 2006.
12. M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. J. Auberton-Herve, J. M. Lamure, T. Barge, F. Metral, S. Trucchi, "'Smart-Cut:' A promising new SOI material technology," IEEE Intl. SOI Conf., pp. 178-179, 1995.