Enhanced high resistivity SOI wafers for RF applications

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 46-47

  Lederer, D ^a   Lobet, R ^a   Raskin, J P ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; ANNEALING; CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC CONDUCTIVITY; GRAIN BOUNDARIES; OXIDES; PASSIVATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; POLYSILICON; Q FACTOR MEASUREMENT; SILICON ON INSULATOR TECHNOLOGY; WAVEGUIDES;

BURED OXIDE (BOX); HIGH RESISTIVITY (HR); RF APPLICATIONS; WAFER BONDING;

SILICON WAFERS;

EID: 16244389280     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Reyes et al., IEEE Trans. Microwave Theory Techn., vol 43 (9), 1995, pp. 2016-2022.
2. D. Lederer et al., IEEE Int. SOI Conf.,2003, pp. 50-51.
3. D. Lederer and J.P. Raskin, submitted to IEEE EDL, May 2004.
4. D. Lederer and J.P. Raskin, Journ. Sol. St. Electron., vol 47, 2003, pp. 1927-1936.
5. H. Gamble et al. IEEE Microwave and G ided Wave Lett.,vol 9 (10), 1999, pp. 395-397.
6. S. Hirae et al., J. Appl. Phys., vol. 51 (2), 1980, pp. 1043-1047.