Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 142-143

  Padilla, Alvaro ^a   Lee, Sunyeong ^a   Carlton, David ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TECHNOLOGY;

DIELECTRIC STACKS; GATE-INDUCED DRAIN LEAKAGE; NVM CELLS; VLSI TECHNOLOGIES;

DRAIN CURRENT;

EID: 51949107159     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588595     Document Type: Conference Paper

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7. C.C. Yeh et al., VLSI Tech. Symp., pp 116 (2005)
8. E. Lusky et al., IEEE-TED 51, 444 (2004)