Assessing SRAM test coverage for sub-micron CMOS technologies

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 24-30

  Kim, Vonkyoung ^a   Chen, Tom ^a  

^a Department of Environmental and Radiological Health Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; PROBABILITY;

FUNCTIONAL FAULTS; MEMORY FAULT PROBABILITY MODEL; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0030644758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)