Protection circuit against differential power analysis attacks for smart cards

IEEE Transactions on Computers

Volumn 57, Issue 11, 2008, Pages 1540-1549

  Muresan, Radu ^a   Gregori, Stefano ^a  

^a UNIVERSITY OF GUELPH   (Canada)

Author keywords

Current flattening; Data encryption; Design studies; Differential power analysis attack; Smart cards

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; ELECTRIC BREAKDOWN; MICROCONTROLLERS; SIGNAL ANALYSIS; SMART CARDS;

CARD MICROCONTROLLERS; CMOS TECHNOLOGIES; CURRENT FLATTENING; CURRENT TRACES; DATA ENCRYPTION; DESIGN STUDIES; DIFFERENTIAL POWER ANALYSIS ATTACK; DIFFERENTIAL POWER ANALYSIS ATTACKS; MICRO-CONTROLLER; POWER CONSUMPTIONS; PROTECTION CIRCUITS; SMALL CHIP AREAS;

ELECTRIC NETWORK ANALYSIS;

EID: 51849112476     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.107     Document Type: Article

References (21)

1. P. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Proc. 19th Ann. Int'l Cryptology Conf. (CRYPTO '99), pp. 388-397, 1999.
2. M. Aigner and E. Oswald, Power Analysis Tutorial, Seminar paper, Inst. Applied Information Processing and Comm., http:// www.iaik.tugraz.ac.at/aboutus/pople/oswald/papers/dpa_tutorial.pdf, 2008.
3. T.S. Messerges, E.A. Dabbish, and R.H. Sloan, "Examining Smartcard Security under the Threat of Power Analysis Attacks," IEEE Trans. Computers, vol. 51, no. 5, pp. 541-552, May 2002.
4. K. Tiri and I. Verbauwhede, "Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '03 , pp. 127-137, 2003.
5. L. Goubin and J. Patarin, "DES and Differential Power Analysis," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '99) pp. 158-172, 1999.
6. P. Kocher, "Timing Attacks on Implementations of Diffie Hellman, RSA, DSS, and Other Systems," Proc. 16th Ann. Int'l Cryptology Conf. (CRYPTO '96), pp. 104-113, 1996.
7. E. Hess, N. Janssen, B. Meyer, and T. Schütze, "Information Leakage Attacks against Smart Card Implementations of Cryptographic Algorithms and Countermeasures - A Survey," Proc. Eurosmart Security Conf., pp. 55-64, 2000.
8. J.-F. Dhem and N. Feyt, "Hardware and Software Symbiosis Helps Smart Card Evolution," IEEE Micro, vol. 21, no. 6, pp. 14-25, Nov./ Dec. 2001.
9. K. Tiri and I. Verbauwhede, "A Digital Design Flow for Secure Integrated Circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1197-1208, July 2006.
10. M. Bucci, R. Luzzi, M. Guglielmo, and A. Trifiletti, "A Countermeasure against Differential Power Analysis Based on Random Delay Insertion," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '05), vol. 4, pp. 3547-3550, 2005.
11. D. May, H.L. Muller, and N.P. Smart, "Non-Deterministic Processors," Proc. Sixth Australasian Conf. Information Security and Privacy (ACISP '01), pp. 115-129, 2001.
12. S.K. Kim, Smart Cards Having Protection Circuits Therein that Inhibit Power Analysis Attacks and Methods of Operating Same, US Patent Application, 2004/0158728, 2004.
13. A. Shamir, "Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies," Proc. Workshop Cryptographic Hardware and Embedded Systems (CHES '00), pp. 71-77, 2000.
14. G.B. Ratanpal, R.D. Williams, and T.N. Blalock, "An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks," IEEE Trans. Dependable and Secure Computing, vol. 1, no. 3, pp. 179-189, July-Sept. 2004.
15. S. Yang, W. Wolf, N. Vijaykrishnan, D.N. Serpanos, and Y. Xie, "Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach," Proc. Conf. Design, Automation and Test in Europe (DATE '05), vol. 3, pp. 64-69, 2005.
16. O. Schneider and D. Uffmann, Circuit Configuration for Generating Current Pulses in the Supply Current of Integrated Circuits, US Patent Application, 2006/7017048, 2006.
17. R. Muresan and C. Gebotys, "Current Flattening in Software and Hardware for Security Applications," Proc. Int'l Conf. Hardware-Software Codesign and System Synthesis (CODES/ISSS '04), pp. 218-223, 2004.
18. R. Muresan, H. Vahedi, Z. Yang, and S. Gregori, "Power-Smart System-on-Chip Architecture for Embedded Cryptosystems," Proc. Int'l Conf. Hardware-Software Codesign and System Synthesis (CODES/ISSS '05) pp. 184-189, Sept. 2005.
19. H. Vahedi, R. Muresan, and S. Gregori, "On-Chip Current Flattening Circuit with Voltage Scaling," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '06), pp. 4277-4280, 2006.
20. W. Rankl and W. Effing, Smart Card Handbook, third ed. Wiley, 2002.
21. ATMEL, Data Sheet: ATmega16(L) Summary, http://www.atmel.com/dyn/ resources/prod_documents/2466S.pdf, 2008.