Power-smart system-on-chip architecture for embedded cryptosystems

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 184-189

  Muresan, R ^a   Vahedi, H ^a   Zhanrong, Y ^a   Gregori, S ^a  

^a UNIVERSITY OF GUELPH   (Canada)

Author keywords

Current flattening in hardware; DES; Power analysis attack resistant architecture; Power smart system on chip; Voltage scaling

Indexed keywords

COMPUTER SIMULATION; CRYPTOGRAPHY; ELECTRIC CURRENT MEASUREMENT; FREQUENCIES; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS;

CURRENT FLATTENING IN HARDWARE; DES; POWER ANALYSIS ATTACK RESISTANT ARCHITECTURE; POWER-SMART SYSTEM-ON-CHIP; VOLTAGE SCALING;

EMBEDDED SYSTEMS;

EID: 27644575545     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1084834.1084883     Document Type: Conference Paper

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