Exploring reconfigurable architectures for binomial-tree pricing models

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4943 LNCS, Issue , 2008, Pages 245-255

  Jin, Qiwei ^a   Thomas, David B ^a   Luk, Wayne ^a   Cope, Benjamin ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CAVITY RESONATORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PIPELINES;

BINOMIAL TREES; FINANCIAL COMPUTATIONS; FIXED-POINT ARITHMETIC; FPGA IMPLEMENTATIONS; PARALLEL PIPELINED ARCHITECTURES; PRICING MODELS; RE-CONFIGURABLE ARCHITECTURE; RE-CONFIGURABLE COMPUTING; RECONFIGURABLE HARDWARE;

PIPELINE PROCESSING SYSTEMS;

EID: 51849091481     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-78610-8_24     Document Type: Conference Paper

References (12)

1. Black, F., Scholes, M.S.: The pricing of options and corporate liabilities. Journal of Political Economics 81, 637-659 (1973)
2. Celoxica, http://www.celoxica.com
3. nVidia, http://developer.nvidia.com/object/cuda.html
4. Constantinides, G.A.: Word-length optimization for differentiable nonlinear systems. ACM Trans. on Design Automation of Elect. Sys. 11(1), 26-43 (2006)
5. Hull, J.C.: Options, Futures and Other Derivatives, 6th edn. Prentice-Hall, Engle-wood Cliffs (2005)
6. Morris, G.W., Aubury, M.: Design space exploration of the European option benchmark using hyperstreams. In: Proc. Int. Conf. on Field Programmable Logic and Applications, IEEE, Los Alamitos (2007)
7. Thomas, D.B., Bower, J.A., Luk, W.: Automatic generation and optimisation of re-configurable financial Monte-Carlo simulations. In: IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (2007)
8. Weaver, N., Markovskiy, Y., Patel, Y., Wawrzynek, J.: Post-placement C-slow retiming for the Xilinx Virtex FPGA. In: Proc. Int. Symp. on FPGAs, pp. 185-194. ACM Press, New York (2003)
9. Xilinx Inc. Virtex 4 FPGA handbook (2004)
10. Xilinx Inc. Floating-point operator v3.0 manual (2006)
11. Wilton, S.W., et al.: The impact of pipelining on energy per operation in Field-Programmable Gate Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 719-728. Springer, Heidelberg (2004)
12. Zhang, G.L., et al.: Reconfigurable acceleration for Monte Carlo based financial simulation. In: Proc. Int. Conf. on Field-Programmable Technology, pp. 215-224. IEEE, Los Alamitos (2005)