An innovative sub-32nm SRAM current sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 47-50

  Makosiej, Adam ^a   Nasalski, Piotr ^a   Giraud, Bastien ^b   Vladimirescu, Andrei ^b,c   Amara, Amara ^b  

^a LODZ UNIVERSITY OF TECHNOLOGY   (Poland)

^b Institut Superieur d'Electronique de Paris ISEP   (France)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MOSFET DEVICES; NONMETALS; SILICON; TECHNOLOGY;

BACK GATES; CIRCUIT PROPERTIES; DOUBLE GATES; DOUBLE-GATE; FULLY-DEPLETED; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES; POWER DISSIPATIONS; PROCESS VARIATIONS; REFERENCE CIRCUITS; SELF-ALIGNED; SENSE AMPLIFIER; TRANSISTOR MISMATCH;

SILICON ON INSULATOR TECHNOLOGY;

EID: 51849086295     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567243     Document Type: Conference Paper

References (7)

1. Kiyoo Itoh, and Riichiro Takemura, "Low-Voltage Limitations of Nano-Scale CMOS LSIs: Current Status and Future Trends", EDSSC, December 2007, Taiwan.
2. E. Seevinck, P. Beers, and H. Ontrop, "Current-Mode Techniques for High-speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SR'"s", IEEE J. Solid-state Circuits, vol. 26, NO. 4, pp. 525-536, April, 1991.
3. Tegze P. Haraszti "CMOS memory circuits"
4. Bastien Giraud and Amara Amara, "Read Stability and Write Ability Tradeoff for 6T SRAM. Cells in Double-Gate CMOS", DELTA, January 2008, Hong Kong H. Wang and P. C. Liu, A Low Power Current Sensing Scheme for CMOS SRAM, IEEE 1996
5. M. Reyboz, T. Poiroux, O. Rozeau, P. Martin and J. Jomaah, "Explicit threshold voltage based compact model of independent double gate (IDG) MOSFET including short channel effects", CEA, Grenoble, France
6. H. Wang and P. C. Liu, A Low Power Current Sensing Scheme for CMOS SRAM, IEEE 1996
7. Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, and Kaushik Roy, "Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure ISSCC, february 2007 San Francisco, CA, USA