ASPA: Focal plane digital processor array with asynchronous processing capabilities

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 1592-1595

  Lopich, Alexey ^a   Dudek, Piotr ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FOCUSING; IMAGE PROCESSING;

DISCRETE-TIME MODE; INTERNATIONAL SYMPOSIUM; PROCESSING CAPABILITIES; PROGRAMMABILITY;

TECHNICAL PRESENTATIONS;

EID: 51749116515     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541737     Document Type: Conference Paper

References (12)

1. Moini, A., Vision Chips or Seeing Silicon. 1999: Kluwer Academic Publishers
2. Dudek, P., Hicks, P.J., A general-purpose processor-per-pixel analogue SIMD vision chip. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2005. 52(1): p. 13-20.
3. Eklund, J.-E., Svensson,C., Astrom, A., VLSI Implementation of a Focal Plane Image Processor-A Realization of the Near-Sensor Image Processing Concept. IEEE Tr. on VLSI Systems,1996.4(3):p.322-335.
4. Komuro, T., Ishii, I., Ishikawa, M., Yoshida, A., A digital vision chip specialized for high-speed target tracking. IEEE Transactions on Electron Devices, 2003. 50(1): p. 191-199.
5. Linan, G., Espejo, S., Dominguez-Castro, R., Rodriguez-Vazquez, A., Architectural and Basic Circuit Considerations for a Flexible 128x128 Mixed-Signal SIMD Vision Chip. Analog Integrated Circuits and Signal Processing, 2002. 33: p. 179-190.
6. Paillet, F., Mercier, D.,Bernard, T.M. Second generation programmable artificial retina. in Twelfth Annual IEEE International ASIC/SOC Conference, 15-18 Sept. 1999. USA: IEEE. p.304-309
7. Lopich, A., Dudek, P. Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. in IEEE ISCAS. 2006. p.3618-3621
8. Lopich, A., Dudek, P. Implementation of an Asynchronous Cellular Logic Network as a Co-Processor for a General-Purpose Massively Parallel Array. in European Conference on Circuit Theory and Design. 2007. Seville, Spain: IEEE. p.84-87
9. Lopich, A., Dudek P. Global operations in SIMD cellular processor arrays employing functional asynchronism. in Sixth Workshop on Computer Architecture for Machine Perception (CAMPS)2006. p.18-23
10. Texas Instruments DSP TMS320C6455-1000. http://focus.ti.com/lit/ ds/symlink/tms320c6455.pdf, May, 2007.
11. Cembrano, G.L., Rodriguez-Vazquez, A., Galan, et.al. R., A 1000 FPS at 128x128 vision processor with 8-bit digitized I/O. IEEE Journal of Solid-State Circuits, 2004. 39(7): p. 1044-1055.
12. Flak,J.,Laiho,M.,Paasio,A.,Halonen, K., Dense CMOS implementation of a binary-programmable cellular neural network. Int. Journal of Circuit Theory and Applications, 2006. 34(4): p. 429-443.