A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 848-851

  Murachi, Yuichiro ^a   Mizuno, Kosuke ^a   Miyakoshi, Junichi ^a   Hamamoto, Masaki ^a   Iinuma, Takahiro ^a   Ishihara, Tomokazu ^a   Yin, Fang ^a   Lee, Jangchung ^a   Kamino, Tetsuya ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a  

^a KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ENCODING (SYMBOLS); TECHNICAL PRESENTATIONS;

H.264/AVC; INTERNATIONAL SYMPOSIUM; PROCESSOR CORES;

MOTION ESTIMATION;

EID: 51749101717     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541551     Document Type: Conference Paper

References (6)

1. K. Kumagai "Systen-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV", ISSCC 2006.
2. S. Warrington "Scalable high-throughput architecture for H.264/AVC variable block size motion estimation", ISCAS 2006.
3. ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, 2003.
4. J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M.Yoshimoto, "A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing," IEICE Trans. Electron., vol.E89-C,no.11, pp.1629-1636, November 2006.
5. ISO/IEC | ITU-T VCEG, Fast Integer Pel and Fractional Pel Motion Estimation for JVT, JVT-F017, 2002
6. Y. Murachi, M. Hamano, T. Matsuno, M. Miyakoshi, M. Miyama, and M. Yoshimoto, "A 95mW MPEG2 MP@HL motion estimation processor core for portable high-resolution video application," IEICE Trans. Fundamentals, vol.E88-A, no.12, pp.3492-3499, Dec. 2005.