Scalable high-throughput architecture for H.264/AVC variable block size motion estimation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3830-3833

  Warrington, Stephen ^a   Chan, Wai Yip ^a   Sudharsanan, Subramania ^a  

^a QUEEN S UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; IMAGE CODING; MOTION ESTIMATION; SCALABILITY; THROUGHPUT;

MOTION VECTOR; PROCESSING ELEMENT ARRAY; VARIABLE BLOCK SIZE MOTION ESTIMATION (VBSME);

VLSI CIRCUITS;

EID: 34547361343     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. T. Wiegand, G. Sullivan, G. Bjontegaard, and A. Luthra, "Overview of the H.264/AVC video coding standard," IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp. 560-576, July 2003.
2. S. Y. Yap and J. V. McCanny, "A VLSI architecture for variable block size video motion estimation," IEEE Trans. Circuits Syst. II, vol. 51, pp. 384-389, July 2004.
3. C. Wei and M. Z. Gan, "A novel SAD computing hardware architecture for variable-size block motion estimation and its implementation with FPGA," in Proc. 5th International Conference on ASIC, 2003.
4. M. Kim, I. Hwang, and S.-I. Chae, "A fast VLSI architecture for fullsearch variable block size motion estimation in MPEG-4 AVC/H.264," in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2005).